What is the problem about "Varify failed"

[Altera_Forum]

Hi, I'm new here. I'm learning about Nios II IDE and follwing the instruction. I have done SOPC Builder, compile, programme, create and build the software 'Hello World!' without any problem. When I'm doing "running the program", I got message "Verify failed" on Console window. The detail message like below: 

 sing cable "ByteBlasterII [LPT1]", device 1, instance 0x00 Processor is already paused  Downloading 00000000 ( 0%) Downloaded 53KB in 0.0s   Verifying 00000000 ( 0%) Verify failed  Leaving target processor paused  Can some one tell me what is wrong whit this? How do I fix this problem?  Thanks for any help. I&#39;m waiting online. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

[Altera_Forum]

The nios2-download tool writes its input data into memory and then reads it back. This message means that the data read back did not match what was written. 

 In your case the memory location which failed to verify is somewhere in the 64k block starting at address 0x00000000. You should check the hardware for that memory to ensure it is correctly set up (right number of wait states, not a ROM or FLASH, etc).

[Altera_Forum]

I got this problem when i set exception address in a tightly coupled instruction memory. I think data couldn&#39;t be read back in this configuration. Is it possible?

[Altera_Forum]

As long as there is a data master connecting to the tightly coupled memory it should be readable (I&#39;m talking about a tightly coupled or avalon connection). 

 Kvinna we need more information to determine what the problem is (for starters what memory type are you downloading to at 0x00000000?). Things to check are: making sure your I/O is properly assigned, clocks in the design are correct, you have your system library project pointing at the memory you expect for compilation, etc....

[Altera_Forum]

Which FPGA device are you targetting? Are you using one of the Nios development boards? Are you using DDR SDRAM?

[Altera_Forum]

I&#39;m using SLS_UP3_SRAM. I have assigned pins and checked them. There are not any problem. When I compile it, I got many warnings.  

CPU is Nios II processor---Altera Corporation Bridge is Avalon Tri State Bridge Communication is JTAG UART Memory is SLS_UP3_SRAM LED_PIO is PIO(parallel I/O) Timer is Interval Timer  Why do I always get "verify failed"?

[Altera_Forum]

Sounds like your memory isn&#39;t working properly.

[Altera_Forum]

If your tristate bus is shared amungst components do a search in the ptf file for your system for "is_shared" under your tristate bridge component. If it&#39;s not set then that could be the problem. I think up on the Altera site under find answers there is a solution for this.

[Altera_Forum]

FYI, I believe that kvinna is using one of the Altera University Program&#39;s UP3 education kits. (I just started playing with one of these.) Users of this kit install a couple extra SOPC Builder components. 

 The components are under "For Quartus II 5.0 and above" at the end of SLS&#39;s up3 documents page (http://www.slscorp.com/up3support/pages/documents.php).  A great UP3 site is altera up3 board resources (http://users.ece.gatech.edu/~hamblen/up3) at Georgia Tech.

[Altera_Forum]

Good call Kerry. I&#39;ve never seen that board before, I guess its a good time to be in school with hardware like that http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif