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Why my HelloWorld program is not working in Nios V/g while working perfectly in Nios V/m?

Benitez__Domingo
683 Views

Hi,

I migrated a golden system reference design (GSRD) for the Terasic DE0-Nano board that is based on a Nios II/e processor to another GSRD for the same board but based on a Nios V/m processor.

A simple HelloWorld program works perfectly in a system integrated by: Nios V/m + SRAM on chip memory + JTAG UART controller.

However, the same HelloWorld program does not work when the Nios V/m core is swapped by a Nios V/g processor.

These are the hw/sw elements used for the practical experience:
- OS: Windows 10
- FPGA software for HW compiling: Quartus Prime 23.1 standard
- BSP & SW Compiling and HW/SW Programming framework: Nios V Command Shell
- Board: Terasic DE0-Nano
- FPGA device: Cyclone IV E

Please, could I have any help?

Attached files:
- DE0_Nano_Basic_Computer.qpf (Quartus Prime)
- nios_system.qsys (Platform Designer, NiosV/g)
- DE0_Nano_Basic_Computer.v
- settings.bsp (Nios V/g)
- HelloWorld.c

During the hardware compilation of the Nios V/g version, some warnings were generated in Quartus. These warnings were not generated for the Nios V/m version.

Info (12128): Elaborating entity "nios_system_intel_niosv_g_0" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0"
Info (12128): Elaborating entity "nios_system_intel_niosv_g_0_hart" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0|nios_system_intel_niosv_g_0_hart:hart"
Warning (10036): Verilog HDL or VHDL warning at nios_system_intel_niosv_g_0_hart.sv(274): object "core_ci_f7" assigned a value but never read
Info (12128): Elaborating entity "niosv_g_core_nios_system_intel_niosv_g_0_hart" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0|nios_system_intel_niosv_g_0_hart:hart|niosv_g_core_nios_system_intel_niosv_g_0_hart:core_inst"
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(303): object "rd_reg_c" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(314): object "wr_fpr_en" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(315): object "wr_fpr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(316): object "wr_fpr_data" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(327): object "W_instr_valid" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(334): object "M0_nxt_seq_pc" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(356): object "W_instr_word" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(464): object "M0_mem_op" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(470): object "E_jmp" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(471): object "E_ebreak_instr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(472): object "E_ecall_instr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(534): object "D_rs3_fpr_val" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(538): object "E_rs1_fpr_val" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(542): object "M0_rs1_gpr_val" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(548): object "M0_multicycle_instr_done" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(618): object "I_expn_type" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(623): object "W_expn_type" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(764): object "M0_instr_incorrect" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(767): object "M0_itag_incorrect" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(796): object "M0_ecc_rs1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(797): object "M0_ecc_rs2" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(800): object "ecc_src" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1049): object "I_ebreak_instr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1050): object "I_ecall_instr" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(812): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1236): truncated value with size 4 to match size of target (2)
Warning (10763): Verilog HDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1698): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10270): Verilog HDL Case Statement warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1698): incomplete case statement has no default case item
Warning (10763): Verilog HDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1711): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10270): Verilog HDL Case Statement warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1711): incomplete case statement has no default case item


Best regards,
Domingo.

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1 Solution
Benitez__Domingo
470 Views

Hi Broddo and Kian,

Thank you very much for your messages.

First of all, the problem was fixed with your help. Now, my HelloWorld program is working perfectly in Nios V/g.

Effectively, the error was in the address map of the peripheral regions. The end address of the on-chip memory is 0x0900_1fff, and the start address of the JTAG UART controller is 0x1000_1000. Then, simply picking a Peripheral Region A Size of 512 KB and a Peripheral Region A Base Address such as 0x1000_0000 allows the "Hello World from Nios V/g" message to be shown on a Nios V juart terminal. In this HelloWorld example, I keep the main memory address region at the start of the memory map, and the memory addresses of my peripherals are further down. However, I think the partition suggested by Broddo should be more efficient.

Kian, I use Quartus Prime 23.1 Standard Edition because my board (DE0-Nano) integrates a Cyclone IV FPGA. So, I used a method like this one. The warnings have not disappeared, but the processor Nios V/g is working as expected. Your suggestion implies using Quartus Prime Pro Edition, with which I cannot generate a programming SOF file for the Cyclone IV device.

Best regards,
Domingo.

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7 Replies
khtan
Employee
618 Views

Hi Domingo,

Thanks for contact Intel Forums. I will look into this issue and get back to you.

Thanks

Regards

Kian

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Broddo
New Contributor I
520 Views

One of the big differences between the m and g is that the g includes instruction and data caches. You have to specify a peripheral region that spans the memory addresses for every IP you have connected to the Nios V/g in order to allow direct access to their configuration registers. Everything outside of this goes through the cache which can cause problems. As you have a JTAG UART controller as part of your design, be sure that you have defined a peripheral region that includes the JTAG UART memory. You can do this in Platform Designer under the niosv/g settings.

NOTE 1: The built-in timer and dm_agent are automatically excluded from the cache so you don't need to worry about including these in your peripheral region

NOTE 2: If you use something like the Generic Serial Flash Interface IP which includes both bulk memory and control registers, the control registers would need to be in your peripheral region but the bulk memory should be outside that region

What I do to simplify this is that I manually specify the memory address of each of my peripherals that aren't instruction or data memory. I keep this at the start of my memory map. Everything else is at least 1MB further down the map. Then I can specify a peripheral region at 0x0000 of size 1MB.

 

 

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khtan
Employee
502 Views

Hi Broddo,

Thanks for sharing your thoughts into this area.

 

Hi Domingo

I talked to the Nios SME over here on this case, first of all there is no Nios V GHRD (work in progress from engineering), was checking whether we have any readily available.

What Broddo mentioned is correct, as Nios V/g have cache, to use peripheral region

  1. Locate the address map of all soft IP.
  2. Pick a start address & end address
  3. Define the address map as peripheral region.

Those warnings is from internal registers which existed since Nios V/g is release which is weird, we also tried replacing directly from Nios V/m to V/g via the replace button (something like this https://www.intel.com/content/www/us/en/docs/programmable/773196/current/hardware-component-37376.html) and didnt get any of those warnings though. Are you using similar method when you changing from V/m to V/g?

 

Thanks

Regards

Kian

 

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Benitez__Domingo
471 Views

Hi Broddo and Kian,

Thank you very much for your messages.

First of all, the problem was fixed with your help. Now, my HelloWorld program is working perfectly in Nios V/g.

Effectively, the error was in the address map of the peripheral regions. The end address of the on-chip memory is 0x0900_1fff, and the start address of the JTAG UART controller is 0x1000_1000. Then, simply picking a Peripheral Region A Size of 512 KB and a Peripheral Region A Base Address such as 0x1000_0000 allows the "Hello World from Nios V/g" message to be shown on a Nios V juart terminal. In this HelloWorld example, I keep the main memory address region at the start of the memory map, and the memory addresses of my peripherals are further down. However, I think the partition suggested by Broddo should be more efficient.

Kian, I use Quartus Prime 23.1 Standard Edition because my board (DE0-Nano) integrates a Cyclone IV FPGA. So, I used a method like this one. The warnings have not disappeared, but the processor Nios V/g is working as expected. Your suggestion implies using Quartus Prime Pro Edition, with which I cannot generate a programming SOF file for the Cyclone IV device.

Best regards,
Domingo.

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khtan
Employee
352 Views

Hi Domingo,

Glad to hear that your program is now working.

 

As for the warnings, I check with the guys over here, and indeed 23.1std have such warnings, even without doing the migration and just instantiating a new Nios V/g will have the warnings. Did not occur in the Quartus Pro though.  Based on assessment done over here, those warnings does not affect the functionality otherwise.

Anyway we have put in a request to our engineering team to fix the warnings in future software version of Quartus Standard.

 

Is there anything else that you wish to ask related to this case? Otherwise I would like to set it to close pending and transition the thread to community support. Thanks for highlighting these warnings out to us.

 

Thanks

Regards

Kian

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Benitez__Domingo
321 Views

Hi Kian,

I have no more questions related to this case. Thank you very much.

Best regards,

Domingo.

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Kenny_Tan
Moderator
247 Views

We (Intel) have “signed-off ” from the post as soln have provided. You can “Bring It Back To Our Attention” by logging in here https://supporttickets.intel.com within the next 15 days for further support. 


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