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We use the nios ii 7.2 multi-processor, using the chip is epc3c25-384c8, cpu clock signal for the 50mhz, using assembly language, when the implementation of the interrupt program, the program execution time is sometimes fast and sometimes slowly, the most time of 70us , the shortest time is 50us, cache for the 4k, we ask to improve procedures for real-time, how to solve this problem? Thanks:confused:
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so didn't say much about the implementation of your multi processor system, but could ist be that the variantion comes from any kind of arbitration logic that controls the access of the different cores and puts one into waiting for a resource while another one is using it ?
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In this system inside, a total of three processors, two of which cpu the program memory sram is external, and the bus is independent, and the other a cpu program memory using fpga internal sram.
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and what about data memories or any other ports or registered shared between these cores ? is there anything they share ?
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In this system, there are three cpu, we call xcpu ycpu and zcpu, xcpu and ycpu between the dual-port ram sharing, ycpu and zcpu are also among the shared dual-port ram.
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Now xcpu require real-time highly, 100us interrupt time, the program run time-critical, can not exceed a certain time
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does this cpu has some kind of caches ?
maybe cache flush when entering interrupt- Mark as New
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Thank you,
When xcpu into the disruption, we use the oscilloscope to see the external sram read signal line, there are signals, as if reading an external program, why read buffer will extend the program execution time? In addition, we found that interruption of proceedings, only a few programs , but the actual execution time of more than a theoretical program execution time, how to solve this problem? This is a nios own shortcomings, or do we design problem?- Mark as New
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THANKS
I question the premise, why enter the interrupt program, the program execution time is sometimes fast, sometimes slow, the problem we have now is not resolved, there is no way in the circumstances, the clock frequency from the original 50mhz raised to 80mhz, also quarts -ii soft would version upgrade from the original 7.2 upgrade to 9.0, but in the case of 80mhz can not run, but the cache from the original 8k reduced to 4k, can run at 80mhz, but this way, reducing the cashe, program execution time and slower, and we feel this is a contradiction, we use the assembly language, can not be used c2h, please help us, thank you http://www.alteraforum.com/forum/showthread.php?t=19389- Subscribe to RSS Feed
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