about component made by user logic

[Altera_Forum]

hello, 

  anyone encounter this problem that a component made by user logic can't run with nios system that has comprised ram and flash and so on?  who can give me some suggestion?   thank you!

[Altera_Forum]

Thanks 

 Sorry I omit another two user logics in my design. The following is the complete structure.  i) Custom Logic I -> FIFO -> IUL (Read) - Nios - IUL (Write) -> FIFO -> Custom Logic II  ii) Custome Logic III -> FIFO -> IUL (Read) - Nios  iii) Custom Logic IV <- Memory <- IUL (Write) - Nios  iv) A PLL provide a systme clk to such logic blocks respectively. They finished the information transmission thru FIFO.   Custom Logic I/II/III are verified that they comply with the timing requirements. However, when Custom Logic IV is added, Custom Logic I/II/III can&#39;t work well. The result is not correct as before. Even Nios refuse to work. I slacken delay requirements between SRAM and Avalon so that Nios can work well now.   I read the timing analyses. Only Custome IV have some critical paths which are not in the normal range. Need I add some timing constraints on such paths?