Dear everyone!
I couldn't understand the "address Behavior" clearly, which is in page 67 of mnl_avalon_spec.pdf.
In my nios2 system, tristate-bridge is used.
1, for SDRAM, connect FPGA-pin-addr0 to SDRAM A0 ,tristate-bridge is used
2, for SRAM, connect FPGA-pin-addr2 to SRAM A0 ,tristate-bridge is used
3, for a 8bit external chip,
connect FPGA-pin-addr0 to chip A0 ,tristate-bridge is used
3, for a 16bit external chip,
connect FPGA-pin-addr1 to chip A0 ,tristate-bridge is used
Is't right?
Could you please tell me what the avalon_bus_fabric do ?
and tell me the detailed dfifference between tristate-bridge and non_tristate-bridge!
Best Regards!
Feiwu
