altera' SDRAM controller

[Altera_Forum]

I used altera's SDRAM controller to read data from my board SDRAM. 

My PLD is the master, and it will access the SDRAM controller. But i find a very strange problem. I test the SDRAM controller,  Write data to sdram, I write 400x32 bit(data bus is 32bit), It will spend 430 cycle, (almost one cycle one data). Read data from sdram. I read C00x32bit, But it spend e2d3 cycle!!!!!!(It means that 12 cycle , one data). The delay is too large.  Does anyone used the sdram controller, do you have the same result ????? Thanks.

[Altera_Forum]

Yes, read the other threads about this. For example this one: 

nios sdram performance (http://www.niosforum.com/forum/index.php?act=st&f=2&t=629&hl=)  You can click on Search and type "SDRAM controller" to find other threads.  C

[Altera_Forum]

Now i find the problem in my design. Because i don't use the pipeline transfer feature of sdram controller. 

Use the readdatavalid pin. I read the pipeline transfer(master read) feature of avalon spec. But i still some questions. 1 the spec don't tell me how to end a transfer.   2 becuase sdram controller will spend some cycle on refreshing . So , if i read data from sdram in each cycle. maybe the fifo of sdram controller will be full.