configuring a new system

[Altera_Forum]

whenever iam creating a new system on SOPC builder and then downloading the .sof file the following message is displayed while running a c/c++ application program 

 Using cable "ByteBlaster II [LPT 1]", device 1, instance 0x00 Pausing target processor: not responding Resetting and trying again: FAILED Leaving target processor paused  Now after doing power-on reset manually then the existing factory loaded program is getting executed  plz help

[Altera_Forum]

sounds to me like your program stalled. Can you debug it? On or off hardware?

[Altera_Forum]

So you downloaded the .sof to the target then tried to launch your application through the IDE – is that correct? 

 Are you sure your hardware is configured correctly? If you are using the dev kit try adding an output that will drive a LED or something that lets you know the processor is running.

[Altera_Forum]

Can you post your Nios Design here?

[Altera_Forum]

Hi all! 

 Maybe you should detail us how you configured the Reset Addess (inSOPC Builder) and where you put .text and .data. (in Nios II IDE).  Your code could be unreachable...  Bye! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

[Altera_Forum]

Hi, 

 I have been experiencing exactly the same problem as Rakesh, however in my case trying to bring up my own board design. The error message doesn&#39;t provide me much help of what to do next!  so... To try and track down things, I&#39;ve re-hashed the design to avoid all external i/o and run entirely within the EP1C12 I&#39;m targetting. So I have (just) enough on-chip RAM for the alt_main "hello world" application - and to set the onchip_RAM block as as my system code/data memory - but *still* this message appears......?  Using cable "ByteBlaster II [LPT 1]", device 1, instance 0x00 Pausing target processor: not responding Resetting and trying again: FAILED Leaving target processor paused  The design downloads okay from Quartus - but from the NIOS IDE when I run-target-hardware that message is all I get?  Does the reset on NIOS need to be issued for it to work after configuration? I only expected to need to use it as my watchdog reset - At the moment it is tied to VCC on the schematic, since I don&#39;t want to debug my external watchdog circuit right now!  Has anybody any ideas what I could try next?  Thanks! ;O)

[Altera_Forum]

Can you describe your resets in more detail (do you have an I/O associated to it, general reset after download, the watchdog is the reset only, etc...) 

 If you have the watchdog feeding the Nios as the reset, then I would "AND" it with a real reset (assuming your resets are coming in active low).

[Altera_Forum]

Hi, 

 At the moment I do not have any reset signal at all. I just set it to vcc on the schematic.  What exactly is the NIOS IDE trying to do via the Jtag port? Is there some trace available to see why it is unhappy?  Thanks!

[Altera_Forum]

Basically the design is dervied from the Nios DevKit reference design - so it will look familiar - http://tinyurl.com/69rnw (http://tinyurl.com/69rnw) 

 The 50Mhz clock is there, because I have some logic producing a flashing LED?  This is quite a riddle, with not too many clues!!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

[Altera_Forum]

Hey!, my design is working now? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ohmy.gif  

 Since my design started with the dev.kit schematic, only thing I noticed was when I double-clicked the sdram-pll..... ...I noticed that it was setup for Stratix (rather than cyclone) - so I set that to cyclone and re-plugged in the parameters?  Could that have been it? It&#39;s nice to see it working - but I&#39;m worried if this is some borderline flakey-thing?  oh well. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

[Altera_Forum]

Did you start off with a Stratix design? If not, what version and build number do you have for Nios? 

 *Edit: Also what ref. design were you using (device, vhdl/verilog, and type (standard, full....etc))

[Altera_Forum]

Back to Rakesh 

 I have a couple questions:  1) Do you have a delay block on the reset going to the Nios (helps the core out of reset since the first few clocks out of the PLL most likely are not in perfect phase yet)?  2) Is your PLL configured for the correct device (like what Joe98 found)?

[Altera_Forum]

i derived my stuff from the Altera Nios2 cyclone design, full_featured. The sdram_pll on that appears to be set for stratix? Have a look and see.

[Altera_Forum]

You are correct. So Rakesh if you are using the same device then this is probably the cause.

[Altera_Forum]

Hi everyone , 

  Iam really happy that it&#39;s working fine now. What I have done is just recompiled the full-featured version of cyclone2 edition reference designs and the I just updated the symbol after compiling. Then it worked fine.But Iam still not sure of the root cause of that problem.

[Altera_Forum]

Do you mean the 1C20 Full Featured reference design? If that&#39;s the case then you probably ran into the same PLL problem that joe98 encountered. So while you were having problems you were using the sof file that came in that project without compiling? Did you have to open the SDRAM PLL and change it to Cyclone for your compile to work or did you simply compile and that worked? 

 Cheers

[Altera_Forum]

I did not change the PLL . But I have re-compiled it and updated the symbol and it just worked.