external 16Bit Slave, shared signals

[Altera_Forum]

I have problems connecting an external chip to NIOSII. 

I used the standard design in SOPC Builder. The chip should work in 16bit  mode and should share all signals, except 'chipselect_n' with the external  SRAM IDT71V416 and the flash am29lv065d. There was already a thread in this forum with the same problem, but no  helpfull answer.   In the standard design, the ext_flash has the description "Flash Memory (Common Flash Interface)". There is another  "Legacy AMD 29LV065D Flash", which is installed in a different folder. (see comonent Description).   I had a look in \components\altera_avalon_cfi_flash\class.ptf:  all signal except "write_n","select_n" are shared   I had a look in \components\altera_nios_dev_kit_stratix_edition_sram2\class.ptf:  all signal except "select_n" are shared  I started with the standard design.    I setup the Chip with Interface to User Logic:  CHIP NAME: HFCE1 Bus Interface Type: Avalon Register Slave  Port Name Width Direction Shared Type  reset 1 input reset address 8 input yes address  write_n 1 input yes write_n read_n 1 input yes read_n data 16 inout yes data chipselect_n 1 input chipselect_n irq_n 1 output irq_n be_n 2 input yes byteenable_n   In Quartus I got the following signals in Block diagram:  be_n_to_the sram_0[3..0] ??? chipselect_n_to_the_HFCE1_0  ext_ram_bus_address[22..0]  ext_ram_bus_byteenablen[1..0] ?? ext_ram_bus_data[31..0] ext_ram_bus_readn ext_ram_bus_writen read_n_to_the_sram_0 reset_to_the_HFCE1_0 select_n_to_the_ext_flash select_n_to_the_sram_0 write_n_to_the_ext_flash write_n_to_the_sram_0  - which are the shared wires ? - to which signal should i connect BE[0..1] of HFCE1   and BE[0..3] of SRAM ? - what is the difference between  - ext_ram_bus_writen  - write_n_to_the_sram_0    - why there is no signal "read_n_to_the_ext_flash" in standard design.  in standard design "ext_ram_bus_readn" is connected to flash_OE   - what`s the difference between "ext_ram_bus_writen" and   "write_n_to_the_ext_flash"   - what`s the difference between "be_n_to_the sram_0[3..0]" and   "ext_ram_bus_byteenablen[1..0]"     Has anyone an working example for an external 16Bit Slave with shared signals  write_n,read_n,byteenable_n ???  thanks

[Altera_Forum]

Hi Fischer, 

 The signals that pop out into an SOPCB system can be decoded as follows (I am borrowing your list of signals):  be_n_to_the sram_0 ??? chipselect_n_to_the_HFCE1_0 ext_ram_bus_address ext_ram_bus_byteenablen ?? ext_ram_bus_data ext_ram_bus_readn ext_ram_bus_writen read_n_to_the_sram_0 reset_to_the_HFCE1_0 select_n_to_the_ext_flash select_n_to_the_sram_0 write_n_to_the_ext_flash write_n_to_the_sram_0  - Anything with "ext_ram_bus" in it is a shared signal for all interfaces on the tri-state bus. This is because ext_ram_bus is the name of your tri-state bridge.  - You need not hook up every signal that is shared (ext_ram_bus) to every pin on every chip; some will not be required (for example, if you're talking to a chip with read/write_n input, or no byte enables). This is device dependant.  - The remaining signals are not shared - they should have the name of a peripheral in the SOPCB system. For example, write_n_to_the_sram_0 means that you have a peripheral attached to your tri-state bridge named "sram_0"... and in its PTF file entry, there is a non-shared write line specified.  - I think the confusion here is because of that separate SRAM interface, sram_0.... just remember that any signals for such interface are not for your chip (the HFCD1)...conversely, any signal (chipselect) with the name HFCE1 is a non-shared pin going to your device as specified.  - If other signals, such as the byte enables, are shared, then the 2-bit BE whose name is "ext_ram_bus..." is what you would connect to your custom SRAM interface.  Please let us know if you need any additional assistance.

[Altera_Forum]

Thanks very much for your reply, 

 I´m a little bit confused about the fact, that a get a signal e.g. read_n_to_the_sram_0, write_n_to_the_sram_0, even if these signals are marked  as 'shared' in the ptf file.  You wrote: - You need not hook up every signal that is shared (ext_ram_bus) to every pin on every chip  is it also true, that I need not hook up every 'none shared' signal to the specific chip, if I can use a shared signal instead ?    I changed the setup of my HFCE1 chip to be_n[3..0], however it only need's two  signals be0_n and be1_n. I did this to get a shared bus "ext_ram_bus_byteenablen[3..0].   So I will connect:  be_n_to_the sram_0[3..0] - ***not used*** chipselect_n_to_the_HFCE1_0 - HFCE1_CS_N ext_ram_bus_address[22..0] - A[22..0] to FLASH,SRAM  and HFCE1 (A1 of bus to A0 of HFCE1, 16 Bit access)  ext_ram_bus_byteenablen[3..0] - BE[3..0] to SRAM (uses BE[3..0])  and HFCE1 (uses only BE[1..0]) ext_ram_bus_data[31..0] - D[31..0] to FLASH,SRAM,HFCE1 ext_ram_bus_readn - FLASH_OE_N, SRAM_OE_N and HFCE1_RD_N ext_ram_bus_writen - SRAM_WE_N and HFCE1_WE_N read_n_to_the_sram_0 - ***not used*** reset_to_the_HFCE1_0 - HFCE1_RESET select_n_to_the_ext_flash - FLASH_CS_N select_n_to_the_sram_0 - SRAM_CS_N write_n_to_the_ext_flash - FLASH_WE_N write_n_to_the_sram_0 - ***not used***   I connected "write_n_to_the_ext_flash" to FLASH_WE_N, because this signal is  marked as 'not shared' in the ptf file.   Is this correct ?