flash programming of Stratix I DSP boards

[Altera_Forum]

We are trying to port NIOSII to the stratix I dsp boards (STD and PRO). One problem so far is to get the flash interface working. Let me start to mention that I have not been able to get details on the content of the EPM7064 config controller, so, some of the time I am guessing my way though the project. 

 a)I made a NIOS II design with a flash device from the list (4/8M 16but wide), resembling the flash on the board as much as possible. b)Took the flash_tests program from the kit and carefully took out all write commands, except the query stuff during identification. You dont want to blow the safe boot! It did not work. It found no flash. c)Added an infinite read loop at the start of the program and started probing the signals with a scope. The line flash_oe# does not have proper switching levels. It goes to gnd ok, but when high its stuck at about 0.7V. The NIOS core is driving this line of course. According to the schematics, only the EPM7064 config controller is touching this line and a 1K to gnd. So my conclusion is that the EPM7064 is not releasing the flash_oe#. This issue is much underlined in the instructions for making a custom flash interface ("Nios II Flash Programmer user guide").  It clear that the SAFE boot image _does_ have the ability to write to the flash and it has access to exacly the same pins as my design. But how is the config controller put aside? The only signals to the config controller which also can be controlled from stratix are: flash_addr, flash_data, flash_OE#, flash_BYTE#, and RESET#  I drive flash_OE#. Put flash_BYTE#=VCC, and wiggle RESET# from a push button. Addr and data are what NIOS core puts out. Any idea what can be the protocol to switch config controller out of the way?  Speaking of nios interface to the flash: The flash has 8MByte(PRO)/4mbyte(std) this requires 23/22 bits of address lines (NIOS_ADDR[23..0]/nios_addr[22..0]. This is comming from the nios core. As the flash is operated with double byte data interface it has a series of address pins (FLASH_ADDR[23..1]/flash_addr[22..1] . So only the upper 22/21 bits are used and connected to the flash as  PRO: NIOS_ADDR[23..1]==FLASH_ADDR[23..1] respectively  std: nios_addr[22..1]==flash_addr[22..1] NIOS_ADDR[0] is unconnected. This must be right is'nt it?   Further info: "Nios II Flash Programmer user guide" points to AN346 but this descibes another config controller (epm7128) which has a completely different interface used on nios kits.  Hope someone have input to these issues as there is a lot of memory on those flashes just waiting to be used!

[Altera_Forum]

1. As far as I know , the logic in EPM7128 in NIos Dev. kit is so large that the EPM7064 can't fit. I don't know how to use flash in DSP Stratix board. :-( And DSP Stratix II board uses the same flash as Nios Dev. kit 

 2. Do u use Nios to access the SSRAM in the board? It's synchronized SRAM,while it is asynchronized in Nios board and in SOPC module. For my poor skill, I haven't solve it yet. Please give me some advice.   thank u.