hardware design for burning nios ii sofaware in flash

[Altera_Forum]

hello everyone: 

I want to run nios ii software in my new fpga board. so I need to place a flash chip on the fpga board. so I want to ask how the flash schematic design? is there any reference design or any design guideline? my fpga chip is 'EP4CE115F29I7', and flash chip is 'S29GL064N'. in my current design, I just connect the signal pins (includes addresses pins:A-1 - A21,data pins: D0-D7, control pins: we,reset,wp/acc,ry/by,ce,oe,byte) to the fpga directly, leave the rfu0-rfu2 and D8-D14 unconnected. can burn the nios ii software to the flash in this hardware design? thanks for any reply. Yefu Chen

[Altera_Forum]

I'm feel sorry for no

[Altera_Forum]

Assuming you have the pinout right and your design meets timing this is all you need to program the flash using the Nios II flash programmer: 

 Nios II with level 1 debug Flash controller Onchip RAM with the exception and reset vectors for the Nios II processor pointing at it System ID (optional but always a good idea to have in your design)  The flash programmer sends the data to the debug module then Nios II writes the data to the flash. So there isn't much hardware needed to do this.