how to use "creat new component"

[Altera_Forum]

hello : 

I have designed a interface about AD574A. and I want the nios to communciate with AD754 through the interface Now I want to fit the interface to the component tool of SOPC Builder . then I use the "creat new component " and add the HDL file of AD574, but I don&#39;t how to choose interface for ports.      the HDL file is bellow:   library ieee; use ieee.std_logic_1164.all;  entity ad574 is  generic(width:integer:=12);  port(D :IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);   CLK ,STATUS : IN STD_LOGIC;--CLK : clock of AD574&#39;s state-machine£¬STATUS:status of AD574 conversion  CE,CS,A0,RC,K12X8 : OUT STD_LOGIC; --AD574&#39;s controlling signal  Q : inout STD_LOGIC_VECTOR(width-1 DOWNTO 0)); end ad574;  architecture behav of ad574 is  type state is (st0, st1, st2, st3,st4);  signal current_state,next_state :state:=st0;  SIGNAL REGL : STD_LOGIC_VECTOR(width-1 DOWNTO 0);  SIGNAL LOCK : STD_LOGIC;   begin  K12X8 <= &#39;1&#39;;   process(current_state,status)  begin  case current_state is  when st0 =>CE<=&#39;0&#39;;CS<=&#39;1&#39;; A0<=&#39;1&#39;;RC<=&#39;1&#39;;LOCK<=&#39;0&#39;;next_state <= st1;  when st1 =>CE<=&#39;1&#39;;CS<=&#39;0&#39;; A0<=&#39;0&#39;;RC<=&#39;0&#39;;LOCK<=&#39;0&#39;; next_state <= st2;  when st2 =>CE<=&#39;1&#39;;CS<=&#39;0&#39;; A0<=&#39;0&#39;;RC<=&#39;0&#39;;LOCK<=&#39;0&#39;;   IF (STATUS=&#39;1&#39;) THEN next_state <= st2;   ELSE next_state <= st3;   END IF ;  when st3 =>CE<=&#39;1&#39;;CS<=&#39;0&#39;; A0<=&#39;0&#39;;RC<=&#39;1&#39;;LOCK<=&#39;0&#39;; next_state <= st4;  when st4 =>CE<=&#39;1&#39;;CS<=&#39;0&#39;; A0<=&#39;0&#39;;RC<=&#39;1&#39;;LOCK<=&#39;1&#39;; next_state <= st0;  when others =>CE<=&#39;0&#39;;CS<=&#39;1&#39;; A0<=&#39;1&#39;;RC<=&#39;1&#39;;LOCK<=&#39;0&#39;;next_state <= st0;  end case;  end process;  PROCESS (CLK) BEGIN  IF ( CLK&#39;EVENT AND CLK=&#39;1&#39;) THEN current_state <= next_state;   END IF;  END PROCESS ;   PROCESS (LOCK) BEGIN  IF LOCK=&#39;1&#39; AND LOCK&#39;EVENT THEN REGL <= D ;  END IF;  END PROCESS ;   Q <= REGL;  END behav;   I have design :  D: export avalon_slave  CLK :clk goble_signal  STATUS :export avalon_slave  CE,CS,A0,RC,K12X8 :export avalon_slave Q:readdata avalon_slave  but when I use the new component "AD574_0" in the nios system , I found the AD574 cannot connect to any slave bus ,and "generate" is failure.  how can I do ?who canhelp me ?

[Altera_Forum]

Generation failing would most likely be due to the component not being connected (never tried it before). You have specified in the Component Editor that this is an Avalon Slave device correct? 

 Here is the Component Editor documentation in case you have not seen it: http://www.altera.com/literature/hb/qts/qt...ts_qii54005.pdf (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf)