impossible to boot ep3c25 from epcs16 - reset_vector problem ?

[Altera_Forum]

Hi, 

 I am developing my first niosII design. It works well when I use a volatile programming file (.sof) but I have issues to program the fpga with an external flash.  I use :  - cycloneIII ep3c25  - flash epcs16 (configuration)  - ssram (nios memory)  - quartus 9.1 sp2  - nios software 10.0  - windows7 x64  The hardware image seems to boot (1 led and 1 screen managed by hw are powered) but NOT the nios. When i try to run the nios manually (run as niosII hw application in eclipse) I have the following error: "Verifying 02401800 (99%) / Verify failed between address / 0x2401800 and 0x240181F / Leaving target processor paused" @02401800 is the epcs_controller base address (=reset_vector @) in the nios.  I don't understand the reason of the failure.  Thanks for helping !   I configure the nios in the sopc builder like that:  - cypress ssram controller  - epcs serial flash controller ("automatically select dedicated AS..." enabled")  - cpu nios : reset_vector = epcs_flash_controller // offset 0x0  exception_vector = ssram // offset 0x20  - other modules: spi_control_port, pio, jtag, sys_clk_timer, sysid...  fpga design/quartus:  - flash pins are set to "use as regular IO"  i use the following method to program the epcs16 :# 1) Convert SOF to Flash sof2flash --input=file.sof --output=hwimage.flash --epcs --verbose# 2) Convert ELF to Flash elf2flash --input=../testBoot.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose# 3) Concatenate cp hwimage.flash hw_sw.flash cat swimage.flash >> hw_sw.flash# 4) Create HexFile nios2-elf-objcopy -I srec -O ihex hw_sw.flash hw_sw.hex  Then i create a .jic file with quartus convert pgm file:  - flash_loader : ep3c25  - hex_data : hw_sw.hex (I try absolute and relative addressing)  I also try without concatenation : file.sof and sw.hex (relative addressing) to create the .jic file.  With the same sopc file I have tested the epcs16 flash with the project template "memory test". both write and read operations work.   Thanks for helping again ! SG.

[Altera_Forum]

I don't think that you should write anything to the EPCS controller base address when downloading the NiosII application. At this address you have a bootloader that is supposed to be read only. 

Did you do anything special to the BSP settings? Check that it is configured to have the application code in the SSRAM (and in the hardware setup, that the NiosII instruction master is connected to the SSRAM).

[Altera_Forum]

Hi Daixiwen, 

 I didn't change anything in the bsp settings. In the linker script tab i have :  - .bss, .exceptions, .heap, .rodata, rwdata, .stack, .text linked in ssram  - .entry linked to reset in epcs_flash_controller The epcs_flash_controller is connected to instruction_master and data_master.  I flash the .jic file by jtag and the harware image successfully boot on power up but not the Nios. Maybe the bootloader (in flash @reset_vector addr) can't be found ? Is there an offset for the bootloader (which implies an offset for the nios reset_vector) ? Is it correct to linked vector_reset into epcs instead of system ram ?  thx

[Altera_Forum]

It looks okay. What is strange is that the memory test template works, but you can't even upload your software directly to memory through JTAG... There must be a difference between your project and the memory test that causes this... 

There isn't any offset and the bootloader is always present, directly in the EPCS controller.  What version of Quartus are you using? Several versions have a bug with the flash converter that puts the software in the wrong place in the EPCS. But this doesn't explain your "verify failed" problem anyway.

[Altera_Forum]

I use quartus 9.1 sp2 and nios 10.0 (i also try nios 9.1). 

I have made a more simple project with only an epcs controller, a sram controller, +sysid, jtag uart and a pio for debug purpose.  I was using the locked signal from an alt_pll to reset the Nios. It was asserted several ms before fpga conf_done signal was asserted so now I use an external reset signal. But it still doesn't work, Nios doesn't boot.  When I program the epcs16 with a jic file (composed by hw & sw), only the hardware boots. After hardware has booted from flash, I can flash the software with Nios IDE, it boots correctly (no more verifying problem...). If I assert (briefly) the external reset signal, the Nios is reseted but never reboots. I both try reset_vector in sram and in flash. I don't understand why the Nios doesn't reboot, especially when the reset vector is in sram ?? Is it because Nios has been downloaded by jtag/ide ?  It works as if the reset_vector always point to a bad memory region...

[Altera_Forum]

Quartus 9.1 sp2 is one of the versions that had some problems with EPCS booting. Have a look at this thread (http://www.alteraforum.com/forum/showthread.php?t=22441). 

 I never tried to flash through a .jic file, but it should work still. As an alternative you can use the Nios flash programmer from the .flash file. I agree that if the reset vector is pointing on the SRAM and you apply an external reset signal to the NIOS cpu after having downloaded your software to SRAM, then the CPU should boot. In some cases I know that the JTAG UART can hang the CPU if no terminal is connected. You could try to remove the UART and just flash a led or something similar from your software to check if it boots. If it still doesn't work, I suggest to use some signaltap probes on the CPU to see what it is doing when getting out of reset.

[Altera_Forum]

I try several nios configurations with small memory needs (reset_vector is in flash in each configurations) and external reset : 

- onchip memory only without jtag -> nios & hard boot without problem  - onchip memory only with jtag&debug -> nios & hard boot without problem  - sram only without jtag&debug -> nios don't boot  - onchip mem (.exception) + sram (all others) + jtag/debug -> nios don't boot.  So I guess there is no problem with jtag. unless quartus bugs are random, i guess there is no problem with quartus too.  The problem seems to be the sram. Hardware could be loaded in sram from flash but not the nios. The nios could be loaded by IDE (with reset_vector in sram) but doesn't support reset...  I will try to downgrade quartus to 9.1 sp1 (unless you think that 10.0 sp1 is better) and maybe use signal tap probes after if no new solutions.

[Altera_Forum]

I also try this configuration : 

- reset_vector in flash, onchip mem (everything in the linker section mappings except reset) + sram (nothing linked to) + jtag/debug -> nios boot !  so it also suggests that sram is responsible for nios boot problems.  nios is not (or not properly) loaded in sram ? some pointers point wrong sram region ?

[Altera_Forum]

Yes it seems to be a problem with the sram. What is strange though is that you can still upload a software to the sram through the IDE, so it seems to be working partially. 

Could you create a project with the memory test template and run it from on-chip memory to test the sram? Are the timing settings correct for the sram?

[Altera_Forum]

I was working on a coworker computer because mine was corrupted (vista, quartus& nios 9.1sp2). I have formated it this morning (w7 x64). I install quartus 9.1sp1, nios 9.1sp1 because after reading several thread I thought it had no bugs (1 is solved : http://www.alteraforum.com/forum/showthread.php?t=19765)... 

 I can't run memory test from on chip memory (not enough memory on fpga - ep3c25) and it doesn't work with sram memory. it is strange because it works with sram a few days ago. I will try without onchip memory at all, maybe I change something in the bsp editor.  is there any documentation about linker ? I don't know what is the function of each field (.bss, .entry...) and I don't find any doc. maybe it could help to understand what occurs in sram.

[Altera_Forum]

Two problems, 

 1. If Quartus II 9.1SP2, DO NOT generate compressed SOF file, use uncompressed instead 2. If NIOS II flash programmer, command line or GUI, DO NOT program EPCS through NIOS II flash programmer, it does not work

[Altera_Forum]

this wikipedia page (http://en.wikipedia.org/wiki/data_segment) explains what those different sections are. 

I wonder if it would be possible to test the memory using the system console tools. But you'll probably have to write your own test script to do that.

[Altera_Forum]

@Waiyung : 

I now use quartus 9.1sp1. I don't use the "compressed bitstream" option. I use command line to convert .elf => .hex then i use quartus convert programming file to generate a .jic.  @Daixiwen : I don't know which commands/tools could be used to test the sram externally. I think it is possible by using jtag to control fpga port, but it don't think altera has developed this functionality. It is more complicated than a simple script. maybe the simple way to test sram is to develop a "simple" routine in vhdl or C (if onchip memory is big enough) which read and write the whole memory. I will read the memory_test template code to see if I can reduce the size and make it fit in onchip_memory.

[Altera_Forum]

What's your SOPC configuration? 

 Reset Vector =? Do you have CFI =?

[Altera_Forum]

I try several configurations : 

- reset_vector -> epcs_flash_controller  - other memory regions in on chip memory (too small for my entire project) => it works  when I replace onchip with sram memory it don't works very well : impossible to boot nios from epcs but hardware image works. I have made several test projects. For some projects it is possible to boot nios with eclipse ide (hw previously loaded with epcs), for others there are some verifying errors when eclipse upload the code...  I am now trying to reduce "memory test" project to make it fit the onchip memory.

[Altera_Forum]

Yes Altera developed this functionnality, it is called system console (http://www.altera.com/literature/hb/qts/qts_qii53028.pdf) tools. There are commands to read and write specific addresses, and you should be able to use them to test the memory. 

For the memory test program, you can try and reduce its size by selecting the small drivers option, removing c++ compatibility (I'm not sure this one will reduce the memory footprint though) and changing the compiler optimization option to "optimize for size".

[Altera_Forum]

I am back again without any clue... 

 Thanks for system console tool info Daixiwen, I didn't know this functionality. I made my program fit the onchip memory (reset_vector -> epcs) (c++, exit, clean_exit disabled / jtag_small_driver / alt_printf), and it ... works. It reads and writes the whole sram (I used 3 data values : 0x55aa55aa, 0xaa55aa55 and data=x for @ddr=x). One interesting thing is that when I use IDE+.sof it works well, but when I use boot from EPCS, nios boot but crash without reaching the end of sram (I know that the program starts and crash during reading/writing sram, but I don't know when). Something is wrong, but what ?  The same program (compiled with all functionalities) in sram which rd/wr onchip works well both with IDE and EPCS methods. Does it works because the program is smaller than my project ? Quartus & bsp editor setting are very similar so I don't understand why my project doesn't work.  I have also checked schematics, connections quality on the board. The more I try different things, the less I see the solution. Maybe I should have asked it for christmas ^^

[Altera_Forum]

Perhaps the stack and/or heap are in sram! 

Check the values of the registers/addresses.

[Altera_Forum]

Sorry for replying late, but I was really bored with the absence of any progress in my issue, so I left it for a few days. 

 I made several modifications and now it works. The entire design (nios+hw) boot from flash. I hope it is not temporary.  These modifications are :  - The connection with sram electronic schematic was taken from the niosII (cycII) eval kit which has the same configuration (epcs, cypress sram). there are some inversion in some address and byte enable pins, so I corrected it in the fpga pin out.   - My prototype board seems to have random problems, maybe due to bad contacts (bad soldering ?), so I made another one.   - In the bsp editor, I disabled some options (which seem to be enabled randomly in new projects ?) : allow_code_at_reset, enable_alt_load... (see http://www.altera.com/literature/hb/nios2/edh_ed5v1_02.pdf page 2-55).  After testing and reading a lot of things, I wonder why altera change so often its softwares versions. Stability and reliability before anything else !!!  Thanks again for answers.  Seb