is there any SOPC and NIOS2 design example of eeprom at93c46

[Altera_Forum]

in my design , i used one chip of eeprom: atmel 's at93c46, this memory 's interface looks like SPI interface. it has CS, CLK,DO and DI , but after reading it pdf document. i found it does accord with SPI protocol. So the SPI interface of SOPC can not be used.  

is there anyone know the example design of this eeprom chip?thanks.

[Altera_Forum]

why do you think that you can't use the spi interface sopc builder provides with this devices ? a quick look into the datasheet from atmel and this at93c46 has a spi interface. 

 or do you mean for AS (active serial) configuration of your fpga, for that you can't use it.

[Altera_Forum]

i read the datasheet of 9346, it is three-wire serial interface, not SPI interface. Atmel has another series SPI interface serial eeprom AT250x0. unfortunately, the two series are not pin compatible. :mad:

[Altera_Forum]

If you open your sopc builder have a look at  

Component Library -> Interface Protocols -> Serial -> SPI (3 Wire Serial)  just add and the configuration dialog opens. Just set it to master, Data width 8 bit MSB first, Clock polarity 0 Clock Phase 0  assuming the added spi was named as spi_0, after generation you should get  Input MISO_to_the_spi_0 connect to AT93C46_DO Output MOSI_from_the_spi_0 connect to AT93C46_DI Output SCLK_from_the_spi_0 connect to AT93C46_SK Output SS_n_from_the_spi_0 connect to AT93C46_CS via inverter  now you have connected the Atmel 93C46 to the SPI available via Nios SOPC

[Altera_Forum]

i paste the read waveform of 9346 from datasheet. from the waveform, if i want to read 9346 a byte , i shoud write 1,1,0,a6-a0,9bit on the mosi, and read 8 bits from miso. if i set the the byte length to 8. the sequence is not compatible to the datasheet.

[Altera_Forum]

you can setup the spi for 17 bit 

shift your data you want to transmit spi_out_data = ( 1,1,0,a6-a0 ) << 8 and when you read data from spi discard to upper 9 bit indata = spi_in_data & 0x0F this should work in this case as transmit and receive is done at the same time, in your case just imagine that after A0 you send 8 time a 0 and every bit before Dn is not needed  the spi ip also has the capability of extending the transmision. this means after all bits have been transmitted and received, the spi ip does not release CS and keeps it in the active state. if you now start the next transmit & receive, another N clock and shifts will be executed. that is usefull if your protocol needs to transfer longer bit streams.

[Altera_Forum]

good idea , let me try......

[Altera_Forum]

i tried and succeed.  

i use 16 bits mode in the 9346's hardware pcb design(org pin tried high). in the sopc, i set the register length to 26, 26=16+6+3+1,   16: word length in the eeprom  6: 9346's address. in 16bit mode, it 's address scope is 0-63;  3: control code;  1: additional bit; set the clock phase to 0 and clock polarity to 0; i paste the file *.h and *.c , i hope it will helpful to someone.

[Altera_Forum]

thats fine, remember "if you can imagine it, you can do it" 

and thats so great that with an fpga you can modify it exactly for your needs.