my code won't execute after a CPU reset

[Altera_Forum]

Hi, 

 I'm trying to do something very simple but since its failing, I think I'm not understanding something fundamental about the IDE's auto-placement of code into memory. I have two memories set up in SOPC builder:  - 8K ROM on-chip  - 128k RAM also on-chip. The reset address is set to the 8k ROM at zero offset, and the exception is set to 0x20 offset also on the 8k ROM. In the Nios IDE system library properties, I put everything into the RAM, (.text,.rwdata....) and there's plenty of room to spare.... I have no off-chip memory right now. The problem seems to be with the auto-generated linker script because when I open the 8kROM.hex file after I build the project, its all zeros from address 0x0-0x20, then at 0x20 (the exception address) it looks like theres some real code there. So it's linking in find the exception code properly, but it isn't linking in the reset code. So I loaded my program up with the debugger and pressed the CPU reset button. Sure enough the debugger stops the process and it's at the reset address like it should be but the instruction its pointing to is 'jump 0x0', when it should actually be trying to jump to '_start'.  I looked a little through other posts on the board and no one else seems to be having this problem, though I didn't scour the board. I checked through the documentation and I couldn't find anything to help me figure out what I am doing wrong. Any ideas? Thanks, drippy

[Altera_Forum]

You can't hit the reset button while running the debugger. That also resets the jtag debug module and everything crashes.

[Altera_Forum]

Ok, I found the answer to this, and apparently it is a bug that Altera is working on. Here's a description of the issue and workaround. 

 http://www.altera.com/support/kdb/solution...05052006_5.html (http://www.altera.com/support/kdb/solutions/rd05052006_5.html)   Solution ID: rd05052006_5 Last Modified: May 23, 2006  Problem  ---------- Why is there no code placed at the reset address of my Nios II system?   Solution  ---------- The Nios® II IDE should insert the .entry section at the reset address you have defined in SOPC Builder if your reset address lies in a volatile memory, such as SDRAM. In order for the .entry section to be placed at the reset address the ALT_NO_BOOTLOADER symbol needs to be defined in the system.h file that is automatically generated by the Nios II IDE.  However, the ALT_NO_BOOTLOADER symbol does not get defined in the system.h file if you have a dual-port RAM in your SOPC Builder system which has one of its ports connected to a master other than a Nios II processor.   As a workaround you can manually define the ALT_NO_BOOTLOADER as a preprocessor symbol for your system library project. To do this in the Nios II IDE, follow these steps:  1. Right click your system library project  2. Select Properties  3. Select C/C++ Build  4. Under the Tool Settings tab, select Preprocessor (under Nios II Compiler)  5. Click on the Add button (it has 3 plus signs)  6. Define a new symbol called ALT_NO_BOOTLOADER  7. Recompile your software project  Now the .entry section will be correctly placed at the reset address.

[Altera_Forum]

In my case the ROM contains a separately compiled custom reset code that was overwritten by the debugger (EDS 9.1sp2) when downloading the program to the target (either for a Run or Debug session). Subsequently, the board did not boot anymore when the reset button was pressed. 

 Because I have pulled out half of my hair before I found out how to avoid it, I post here the steps to follow : - right-click on your bsp project and select "Nios II/BSP Editor..." - in tag Settings, select "Settings/Advanced/hal/linker" - uncheck "allow_code_at_reset" and "enable_alt_load"   P9