nios debug freezing

[Altera_Forum]

Normally,my design works well, but sometimes I do a little change in the fpga design,such as put a signal on an output pin for test. run nios ide. after nios finish downloud SW and jump in debug windows, there is no response again.no waring no error. software can not enter main() . if restored old desgin, everything is ok. we desgin the old prj in q4.1 and nios 4.1. all of the design are write by vhdl and verilog. 

nowadays, we compile the old one in q5.0 and nios5.0. so... give me a hand.

[Altera_Forum]

It's not unheard of that small design changes affect borderline timing on some other component (memory, I/O) to the point where the program crashes or the debugger can't communicate any more. 

 First thing to check might be the timing on RAM, if you have that.

[Altera_Forum]

--- Quote Start ---  originally posted by queisser@Aug 29 2006, 12:25 AM it&#39;s not unheard of that small design changes affect borderline timing on some other component (memory, i/o) to the point where the program crashes or the debugger can&#39;t communicate any more.  first thing to check might be the timing on ram, if you have that. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=17910)  --- quote end ---    --- Quote End ---    system clk is 85Mhz. i download a test SW to on chip ram. it will check external memory chip such as ssram,sdram flash, gmac.... the result is good and no error find. then i download main prj to external memory space again, it is no response after jump to debug windows.  external memory work at 85Mhz and external gmac at 125Mhz. all of these memory space can read and write. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif