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How can I interface nios to the fifo outside the nios?
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Hi,todayss,
I remembered you had seeked for help on the forum about the problem of transplantation of uC/OS II to Nios based on APEX20KE board,right? Have you tackled that?- Mark as New
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Hi
freezy2000 I haven't handle it yet.My project may work without it though a little difficult. And now my problem is about the interface between nios and FIFO logic,without it my project can't run. Could you help me?- Mark as New
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You can get answer in AN333.You should implement a Avalon slave bus to handle fifo.
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Yes,to add a FIFO to your system,you need to resort to Avalon bus.
You can look over some docs of that.I think that may be helpful.- Mark as New
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Have a look at Mike DeSimone's FIFO IP over in the "Post Your Own IP" section.
I've installed it, but haven't deployed it yet. I'm still banging away on interrupting on AlmostFull from an external fifo and burst reading the contents using an avalon dma. It works great except it's never perfect. I get 2-4 misses or double reads every time I empty the 480 32 bit words out of a 512 word fifo. I've just about got the culprit nailed using SignalTap. But if I can't overcome, then the next thing to try is Mike's IP. Ken- Mark as New
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If it's a simple fifo then put a fifo outside, create a custom interface to the fifo (uses the avalon bus), bypass cache if you are using NIOS II/f, and read like you do from any other register. I've never taken a look at the IP that's posted in the forum, but if it sounds easy enough to use then try it, otherwise the solution I rambled off should do the trick too.
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--- Quote Start --- originally posted by kenland@Aug 23 2004, 09:06 AM have a look at mike desimone's fifo ip over in the "post your own ip" section.
i've installed it, but haven't deployed it yet. i'm still banging away on interrupting on almostfull from an external fifo and burst reading the contents using an avalon dma.
it works great except it's never perfect. i get 2-4 misses or double reads every time i empty the 480 32 bit words out of a 512 word fifo.
i've just about got the culprit nailed using signaltap. but if i can't overcome, then the next thing to try is mike's ip.
ken --- Quote End --- Kenland, Did you ever get the FIFO problem solved? I keep getting the same problems (double reads and misses)? Thanks.
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Hi Narab1,
Yeah, I got it working. You can tell by all the blood http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif On NiosII: "Create New Component" a port with a IRQ signal and others. (my class.ptf follows) Set the IRQ very high priority (like 0 or 1) If you have any other ISR's turn on nested interrupts, or raise the size of the fifo above the IRQ point until you're ISR gets called in time. Good Luck! Ken Here is my FIFO spec. NFIFO : scfifo WITH ( INTENDED_DEVICE_FAMILY = "Cyclone", (works on Stratix too) LPM_WIDTH = 36, LPM_NUMWORDS = 512, LPM_WIDTHU = 9, LPM_TYPE = "scfifo", LPM_SHOWAHEAD = "ON", OVERFLOW_CHECKING = "OFF", UNDERFLOW_CHECKING = "OFF", USE_EAB = "ON", ADD_RAM_OUTPUT_REGISTER = "ON" ); Hook the used[] bits up to an and gate to create an appropriate IRQ into the NiosII. Register your ISR to dma from the fifo (hooked into your Component as well) into memory or whatever. Here is my Component's class.ptf: # # This class.ptf file built by Component Editor# 2005.01.25.15:22:30# # DO NOT MODIFY THIS FILE# If you hand-modify this file you will likely# interfere with Component Editor's ability to# read and edit it. And then Component Editor# will overwrite your changes anyway. So, for# the very best results, just relax and# DO NOT MODIFY THIS FILE# CLASS scan_in { MODULE_DEFAULTS { class = "scan_in"; class_version = "1.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "0"; } PORT_WIRING { } SIMULATION { DISPLAY { } } SLAVE SCAN_IN { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Width = "2"; Address_Alignment = "dynamic"; Data_Width = "32"; Has_Base_Address = "1"; Has_IRQ = "1"; Setup_Time = "0cycles"; Hold_Time = "0cycles"; Read_Wait_States = "1cycles"; Write_Wait_States = "1cycles"; Read_Latency = "0"; Max_Pending_Read_Transactions = "1"; Is_Printable_Device = "0"; Is_Memory_Device = "1"; } PORT_WIRING { PORT address { width = "2"; width_expression = ""; direction = "input"; type = "address"; } PORT RE { width = "1"; width_expression = ""; direction = "input"; type = "read"; } PORT readdata { width = "32"; width_expression = ""; direction = "output"; type = "readdata"; } PORT dataIRQ { width = "1"; width_expression = ""; direction = "output"; type = "irq"; } PORT CS { width = "1"; width_expression = ""; direction = "input"; type = "chipselect"; } } COMPONENT_BUILDER { AVS_SETTINGS { Setup_Value = "0"; Read_Wait_Value = "1"; Write_Wait_Value = "1"; Hold_Value = "0"; Timing_Units = "cycles"; Read_Latency_Value = "0"; Max_Pending_Read_Transactions_Value = "1"; Address_Alignment = "dynamic"; Is_Printable_Device = "0"; Is_Memory_Device = "1"; external_wait = "0"; } } } } USER_INTERFACE { USER_LABELS { name = "SCAN_IN"; technology = "User Logic"; } WIZARD_UI the_wizard_ui { title = "SCAN_IN - {{ $MOD }}"; CONTEXT { H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters"; M = ""; SBI_SCAN_IN = "SLAVE SCAN_IN/SYSTEM_BUILDER_INFO"; } PAGES main { PAGE 1 { align = "left"; title = "scan_in Settings"; layout = "vertical"; TEXT { title = "Built on: 2005.01.25.15:22:30"; } TEXT { title = "Class name: scan_in"; } TEXT { title = "Component name: SCAN_IN"; } TEXT { title = "Component Group: User Logic"; } } } } } CB_GENERATOR { top_module_name = ""; emit_system_h = "0"; HDL_FILES { } } COMPONENT_BUILDER { CACHED_HDL_INFO { # cached hdl info, emitted by cbGuinevereApp.CBFrameRealtime.getDocumentCachedHDLInfoSection:130 # used only by Component Builder } HDL_PARAMETERS { # generated by cbDocument.CBDocument.getParameterContainer:348 # used only by Component Editor } SW_FILES { } built_on = "2005.01.25.15:22:30"; } ASSOCIATED_FILES { Add_Program = "the_wizard_ui"; Edit_Program = "the_wizard_ui"; Generator_Program = "cb_generator.pl"; } }- Mark as New
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Thanks KenLand. I appreciate it.

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