Hi mates!
I have a question about when it is necesary to re-generate my niosII system. I am writting my own component to connect it through Avalon to the uP NiosII. Every time I change the verilog/vhdl code is it necesary to re-generate the sopc-system? It is supposed that the changes in the code don't affect to the component interfaces. Many thanks.链接已复制
4 回复数
