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re-generate sopc system

Altera_Forum
名誉分销商 II
1,178 次查看

Hi mates! 

 

I have a question about when it is necesary to re-generate my niosII system. 

 

I am writting my own component to connect it through Avalon to the uP NiosII. Every time I change the verilog/vhdl code is it necesary to re-generate the sopc-system? 

 

It is supposed that the changes in the code don't affect to the component interfaces. 

 

Many thanks.
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Altera_Forum
名誉分销商 II
497 次查看

If there is no change to the interfaces then it should not be necessary to regenerate the SOPC system.

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Altera_Forum
名誉分销商 II
497 次查看

If there are no changes in top signals (e.g. new signals, signal removal, width change, etc), then the SOPC system can be left as it is, but You have to resynthesize the code.

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Altera_Forum
名誉分销商 II
497 次查看

re-synthesize means re-compile? 

 

Thank you
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Altera_Forum
名誉分销商 II
497 次查看

basically - yes.

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