Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
12748 Discussions

section .text overlaps section .entry

Altera_Forum
Honored Contributor II
2,660 Views

Hello, 

 

I defined an internal ROM with 16kBytes (0x00c08000-0x00c0bfff) and an internal RAM with 2kBytes starting at address 0x00c02000. 

Small C library and Reduced Device Drviers are used. 

When compiling the design the linker puts out the following error: 

 

section .text [00c08000 -> 00c09223] overlaps section .entry [00c08000 -> 00c0801f] 

 

In my opinion there is enough space left in the internal ROM, because the software seems to use only from ..8000 to ..9223. 

Why can't the linker separate the .text section from the .entry section!?!??!? 

Any ideas or hints!?!??! 

 

Thanks 

 

damc
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
1,260 Views

hi demc, 

 

did you check the autogenerated linker script generated.x in ...syslib\debug\system_description\ for more information about memory assignments? 

 

--wolf
0 Kudos
Altera_Forum
Honored Contributor II
1,260 Views

You can also add following options to your project setting under C/C++ build -> Linker ->General 

 

-Xlinker -Map -Xlinker map.txt 

 

This will produce a detailed map file in same directory with your .elf file so you can take a closer look where your data and code is located.
0 Kudos
Altera_Forum
Honored Contributor II
1,260 Views

Hello pfab, 

 

the generated.x file looked ok for me ... 

 

 

Hello keijo, 

 

in the map.txt file it looks really like that the section .text and .entry start both at the same address 0x00c08000. So they overlap ;-(, the linker was right. 

 

 

I just changed the internal ROM address to 0x00000000 and ... it worked, no overlapping anymore. 

Section .entry starts now at 0x00000000 and section .text starts at 0x00000020. 

 

Remains the question, is it working now because I regenerated and recompiled everything or because I changed the ROM address (and it's a bug) .... 

 

So thanks for your hints and help!!! 

 

damc
0 Kudos
Altera_Forum
Honored Contributor II
1,260 Views

What did you specify as reset and exception addresses in SOPC builder? There should be 0x20 offset in the exception address. If you did have the offset then my suggestion is that regeneration cured your problem.

0 Kudos
Altera_Forum
Honored Contributor II
1,260 Views

As reset address I specified the internal ROM, as exception address the internal RAM. 

In both of my versions. 

Sorry, I didn't checked the offset, the SOPC-Builder has done this automatically and also correct in the past...
0 Kudos
Reply