unexpected input at Nios core!

[Altera_Forum]

Hi all, 

I have got an unexpected input at my NIos core, and I dont know what its functionality. it is an: E_en_to_the_cpu_0 input. Can anybody tell me something about this?  thanx

[Altera_Forum]

NIOS I or NIOS II? 

 When you say you have an input do you mean it's showing up on the left side of the symbol? If so which part of the symbol does it show up in (the symbol gets subdivided with lines to symbolize different parts in the SOPC system).

[Altera_Forum]

Semir, 

 By chance are you using any kind of pre-release or beta? We screen for such signals 'popping out the top' quite thoroughly in anything nearing release although its not uncommon in our development work to see them as new logic is being added (basically it means that an internal signal is not driven by other logic as it should be).  If you are using a released version (1.0/1.01) of the Nios II kit I'd reccomend that you contact Altera support and explain the problem along with your system's ".ptf" file so that they can file a report on this.

[Altera_Forum]

I thought this sounded familiar. 

 This bug slipped into version 1.01 of the JTAG Debug Module. It only shows up when using the debug module with the Nios II/e core.   It's fixed in version 1.1, and the workaround for version 1.01 is to connect the signal to logical 1 or VCC.

[Altera_Forum]

I just ran into this myself. The E_en_to_the_mynios2 signal showed up after I altered the size of my SRAM module (and generated). When it happened the other day, I was changing the debug module settings, but I was able to make it go away somehow and still retain the debug module. This time it looks will not go away unless I have no debug module. Oh well. When is that 1.1 due anyway?

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  Oh well. When is that 1.1 due anyway?[/b]  --- Quote End ---    "Near the end of the year." (According to Alan.)  Kerry