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Hardware Performance Counters on Alder Lake 12th Gen

BMorgan1296
Beginner
727 Views

Hi,

 

I believe the performance counter interface has changed for the 12th gen processors.  How do we access these now?

 

MSR 0xE01 should be the global counter control, however Intel's msr-tools package 'rdmsr' command no longer allows writing to this register to enable the counters.

 

As well, MSR 0x396, which should report how many uncore slices exist now reports 0x1000A for the i9-12900KF. This processor should have 10 (0xA) slices (8 for P cores, 2 for the E core clusters), so I am not sure how to interpret this MSR anymore.

 

The Intel Core uncore performance monitoring manual is about 6 years out of date (and relevant to 6th generation Core processors only), and there has been no updates to the combined Software Development Manual in several months either.

 

What's the go?

 

Cheers.

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AndrewG_Intel
Moderator
704 Views

Hello @BMorgan1296

Thank you for posting on the Intel® communities.


Could you please provide us with the following details in order to check this further?

1- Are you referring to Intel® Performance Counter Monitor?

2- When you said "Intel's msr-tools package 'rdmsr' command", do you mean the resources in this repository? GitHub intel / msr-tools

3- Is this the manual that you are following? 6th Generation Intel® Processor Family Uncore Reference Manual.

4- Why do you need this information? What is the impact level? Are you designing a product or developing software using Intel® Products? Please provide details.


Best regards,

Andrew G.

Intel Customer Support Technician


BMorgan1296
Beginner
692 Views

Hi @AndrewG_Intel ,

 

To answer your questions:

1- I am not referring to Intel Performance Counter Monitor. I am referring to in-built hardware performance counters which are accessible using RDPMC, RDMSR and WRMSR CPU instructions. I assume Intel PCM would use these at a lower level.

 

2- Yes that repository is the one I am using to query initialisation registers to enable the hardware counters.

 

3- Yes, I am following this manual. I can not enable MSR_UNC_PERF_GLOBAL_CTRL. As well, MSR_UNC_CBO_CONFIG does not relate to its description in this manual anymore. I am unsure how to interpret "0x1000A" as the number of LLC slices.

 

4- I am developing my own performance counter interface in C by accessing these low level counters to perform micro-benchmarks of program functions with as little overhead as possible.

AndrewG_Intel
Moderator
639 Views

Hello BMorgan1296

Thank you for your response and for these details.

Please allow us to review this further and we will be posting back in the thread as soon as more information is available.


Best regards,

Andrew G.

Intel Customer Support Technician


BMorgan1296
Beginner
632 Views
Thanks, looking forward to your response.
AndrewG_Intel
Moderator
587 Views

Hello BMorgan1296

Thank you for your patience in this matter.

After checking this further, our recommendation is to refer to Intel® Developer Zone where you may find resources and help for development areas using Intel® Products. You may refer to this link for Contact Options and Support Options.

Having said that, we will proceed to close this inquiry now. Thank you for your understanding.


Best regards,

Andrew G.

Intel Customer Support Technician


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