Questions about Integrated memory controller and Intel ME.

[idata]

Hi. all I have two questions on the integrated memory controller (IMC) inside the CPU package.

I've read several Intel manual and questions about the IMC but cannot figure out its internal perfectly.

The first question is about its independent clock inside the IMC and overclocking.

I've already read these two questions and following answers.

This link says...

If you use a memory that run faster than what the processor was design for, you will need to overclock the processor by enabling the XMP mode on the motherboard BIOS, if you run a memory faster than 2133MHz with this processor we don't know at what speed the IMC will run.

For example if you run it a memory at 3200MHz perhaps the processor will run it at 2600MHz or less or maybe a little more, perhaps it will run at 3200MHz but I cannot guarantee that because, even though this is an unlock processor Intel has not tested the processor at that speed or out of the processor specifications.

Here is my first question: If the clock of the IMC is not increased linearly as the memory ratio increase (2133MHz -> 3200MHz). Does it mean that IMC cannot fully utilize (support) the performance of the DRAM because the IMC clock cannot be overclocked as much as memory ratio??

The Second question is about simultaneous requests on IMC and its support on brand-new CPU models such as skylake and kaby-lake

http://www.intel.com/Assets/PDF/datasheet/323341.pdf http://www.intel.com/Assets/PDF/datasheet/323341.pdf

Following the above link, "The memory controller can operate on up to 32 simultaneous requests(reads and writes)"

I would like to know how many simultaneous requests are supported in skylake and kabylake CPUs.

I've already checked the 6th and 7th generation of the Intel CPU datasheet, but I cannot find any information.

The last question is about the Intel management engine (ME) and memory controller.

It seems that Intel ME operates independently and isolated from other hardware components inside the package.

The question is If some part of the memory controller does not work properly, does it mean that Intel ME cannot work anymore?

Or does the Intel ME has the separated SRAM or storage?

I've heard that Intel ME exist to analyze some hardware problems or reboot the system remotely, or even sniping memory packet, etc.

I would like to know which hardware components are the prerequisites to operating the Intel ME.

**If possible please give me the link that explains the internal of the IMC or ME **

Warm regards

Jaehyuk

[idata]

Hello Jaehyuk.Lee:

To answer your inquiry, I just wanted to let you know that we will do further research on this matter in order to try to provide the most accurate response in regard to the information you are requesting. But before we do that, I just wanted to ask if you need this information for 7th and 6th generation processors or you are interested in any other generation as well? Any further questions, please let me know. Regards Alberto

[idata]

Hi Alberto

Thanks for your reply

I would like to know about the 6th generation processor most.

Best regards

[idata]

Hello Jaehyuk.Lee:

You are welcome. Thank you very much for providing that information. Perfect, we will start the research in order to try to provide the information you requested. Any questions, please let me know. Regards Alberto

[idata]

Hello:

Thank you very much to Ronin for the information posted previously. To Jaehyuk.Lee: The following are the answers in regard to the information you requested:I would like to know how many simultaneous requests are supported in skylake and kabylake CPUs? Not specified since the memory controller on both KBL and SKL has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next. The most efficient request is picked from all pending requests and issued to system memory Just-in-Time to make optimal use of Command Overlapping. More info: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-1.pdf http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-1.pdf (page 23) If some part of the memory controller does not work properly, does it mean that Intel ME cannot work anymore? Not necessarily. At system initialization, the Intel® ME loads its code from system flash memory. This allows it to be up and running before the main Operating System is started. Therefore, if there is a problem with the IMC (system memory) Intel ME can still initialize. Does the Intel ME has the separated SRAM or storage? Answer: Yes, read below for further details. I would like to know which hardware components are the prerequisites to operating the Intel ME? The Intel® Management Engine (ME) is an embedded microcontroller (integrated on Intel chipsets) running a lightweight microkernel Operating System that provides a low-power, OOB (Out Of Band) execution engine for management services. Additionally a fundamental feature of the Intel® ME is that its power states are independent of the host OS power states. This allows it to be up and running when the Microprocessor and many other components of the system are in deeper sleep states. As a result, the Intel® ME can be a fully-functioning component as soon as power is applied to the system. This allows it to respond to OOB commands from the IT management console without having to wake up the rest of the system, thereby reducing power consumption significantly. This opens the door for a large number of innovative, low-power, secure OOB usages that result in a significant reduction in TCO (Total Cost of Ownership Any questions, please let me know. Regards Alberto

[idata]

Hello Jaehyuk.Lee:

I just wanted to check if the information posted previously was useful for you and if you need further assistance on this matter? Any questions, please let me know. Regards Alberto

[idata]

Hello alberto_intel :

I really appreciate all your kind reply.

Especially the link was useful to understand how the IMC works.

I think your provided information is enough to resolve my questions and curiosities.

I will let you know If I have further questions.

Warm regards

Jaehyuk.

[idata]

Hello Jaehyuk.Lee:

Thank you very much for letting us know that information. Excellent, It is great to hear the information provided was useful for you. No problem at all, any other inquiry, do not hesitate in contact us again. Regards Alberto

[CCris2]

Hi Jaehyuk.Lee ,

When you enable XMP the processor keeps its base clock bclk , only IMC changes base frequency - bclk or bclk+33.33 and multiplier ( IMC has different multiplier then the CPU ). The IMC for DDR 2133 runs at 1066.66 MHz, because the memory in fact runs at 1066.66 Mhz and being Dual Data Rate is 1066.66 * 2 . IMC frequency in this case is (100+33.33)*8 = 1066.66 .

Intel ME has 2 parts. The firmware that is a software addition, as part of the bios, and it comes incorporated and can be updated with it, and the Intel ME driver.

Intel ME can control some aspects of the CPU, like bugs at hardware level or power states of the CPU components.

On the corporate versions of CPUs, it gives the option of remote management from network.

I gave you those small details, about what you asked,.from experience and some documentation over internet.

If you want even more details, I think Alberto will point you to the right documentation, as he knows better where it should be

Have a nice day.

[AHanu]

Hello,

I am looking for Compliance and Testing Guide for Intel ME Kabylake platform.

Appreciate your help to know if this document is available and how i can get it

[idata]

Alex@Nuvoton: In that case please submit your inquiry on a new thread, the reason for that is that every scenario is different, even if the same product is being used, so, for us to better assist you to try to provide the information you are looking for, please submit a new thread:

https://communities.intel.com/community/tech https://communities.intel.com/community/tech Let me apologize for any inconvenience. Regards,Alberto R