I am trying to read DIMM temperature values from a register within the processor.
According to the datasheet 6th Gen Intel Core/Pentium/Celeron/Xeon Processors EDS, Volume 2 (https://cdrdv2.intel.com/v1/dl/getcontent/334408), there is a DDR register with offset 58B4h that reads the Per-DIMM temperature values. It is located on Bus 0, Device 0, and Function 0. It is within the MCHBAR registers section of the datasheet.
So, I have the Bus, Device, Function, and Offset of this register but I was struggling to find the base address of this.
In section 3.12 I found the "Host Memory Mapped Register Range Base(MCHBAR)" with offset 48h. It says that bits 38:15 correspond to the "base address Host Memory Mapped configuration space"; so I was thinking that reading bits 38:15 would give me the base address for all the MCHBAR registers. Is that correct?
When I read bits 38:15, I get 0x1FDA2, and I try using it with the offset 0x58B4, but only read a value of 0, so I'm thinking I'm doing something wrong.
I am using a software library with a method that takes in Bus, Device, Function, Base Address, and Offset to read registers in the PCI space, so I am assuming I simply having something wrong with the address.
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