SIMD register layout across different processors

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Hi All,

I’m a CMU student doing research on SIMD performance across different Xeon processor generations. 

I am looking for some type of documentation that describes the location SIMD registers across different cores. Does every core have the same SIMD registers? If not what happens if a program running on a core calls an assembly command that corresponds to a register that is not on that core? Is it possible to have threads be bottlenecked on SIMD registers if there are more threads running very vectorized workloads than there are cores with SIMD registers? Is this layout of SIMD registers different across different Xeon processors and generations? (I only really need to know for Xeon but am curious about other processors as well lol)

Like I can’t find any documentation that indicates where the SIMD registers are physically located. I would assume that they are are identical on every core in the processor, but I cant find any documentation that says that and if they’re not what is the SIMD behavior on other cores in the system? 

Thanks!!

[IntelSupport]

Hello New User,

Thank you for posting your question on this Intel® Community.

Depending on the documentation requested, it may not be published and is usually protected under a Non-Disclosure Agreement (NDA). However, we are currently reviewing your request.

To better assist you, we would like to know if you are currently developing software or working with a specific program.

Wanner G.

Intel Server Specialist

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I am developing a piece of software and I am turning vectorization on and off for TBB.

[IntelSupport]

Hello Beginner,

Thank you for your response. 

Please allow us to look into this request.

Wanner G.

Intel Server Specialist

[IntelSupport]

Hello Menu,

I would like to provide an update on this thread.

Our recommendation is that you review the section 2.2.7 SIMD instructions within Volume 1 of the Intel Software Developer Manual located here: https://software.intel.com/content/www/us/en/develop/articles/intel-sdm.html.

Also, I would like to share the following web page: Intel® C++ Compiler 19.1 Developer Guide and Reference.

Link: https://software.intel.com/content/www/us/en/develop/documentation/cpp-compiler-developer-guide-and-reference/top/compiler-reference/intrinsics/intrinsics-for-intel-streaming-simd-extensions-intel-sse/details-about-intel-streaming-simd-extensions-intrinsics.html

If you have additional questions or the above web content does not address your software development questions, our recommendation is that you submit your questions to one of the following Intel Software Developer Community forums:

Intel® ISA Extensions

https://community.intel.com/t5/Intel-ISA-Extensions/bd-p/isa-extensions

Intel® Moderncode for Parallel Architectures

https://community.intel.com/t5/Intel-Moderncode-for-Parallel/bd-p/moderncode-parallel-architectures

I hope you find this information helpful.

Wanner G.

Intel Server Specialist