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While number of execution units (ALUs, FPUs, VEs) in modern CPU cores is great, there are other resources still in limited amount, like decoder-translator, scheduler, registers, branch prediction unit, L1 caches. Logical CPU still needs some physical hardware, like own APIC and port on memory controller. Also, it is hard to get such sustained load of atomic instructions with no conflicts on EU type and shared data, especially on desktops. IBM Power architecture gets to SMT level of 8, but die size and TDP costs per core was (and still) tremendous.
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While number of execution units (ALUs, FPUs, VEs) in modern CPU cores is great, there are other resources still in limited amount, like decoder-translator, scheduler, registers, branch prediction unit, L1 caches. Logical CPU still needs some physical hardware, like own APIC and port on memory controller. Also, it is hard to get such sustained load of atomic instructions with no conflicts on EU type and shared data, especially on desktops. IBM Power architecture gets to SMT level of 8, but die size and TDP costs per core was (and still) tremendous.
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Hello JFFulcrum
Thanks for your contribution this will help others.
Regards,
Caesar B.
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