Xeon Phi™ Coprocessor 7120P hyperthreading

[cb4letni]

Dear All,

Looking at the product page for the subject processor, I see no mention of hyperthreading.

https://ark.intel.com/content/www/us/en/ark/products/75799/intel-xeon-phi-coprocessor-7120p-16gb-1-238-ghz-61-core.html

Thus, can I correctly assume that there is no hyperthreading available for the subject processor?

Please advise.

Best,

CB

[JoseH_Intel]

Hello cb4letni,

Thank you for joining the Intel community

As you correctly state none of the Xeon Phi Coprocessors from the x100 (Knights Corner) and x200 (Knights Landing) families support hyperthreading.

For more details you can check the product brief here: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-phi-processor-product-brief.pdf

Regards

Jose A.

Intel Customer Support

For firmware updates and troubleshooting tips, visit:

https://intel.com/support/serverbios

[JoseH_Intel]

Hello cb4letni,

I am just following up to double-check if you found the provided information useful. If you have further questions please don't hesitate to ask. If you consider the issue to be completed please let us know so we can proceed to mark this ticket as closed. This support interaction will be marked as resolved automatically in the next 3 business days if no activity is received. 

I will try to contact you back on next Monday 14th unless you prefer a different date.

Regards

Jose A.

Intel Customer Support Technician

[cb4letni]

Dear Jose,

Thanks for following up. Since my original post, I've encountered the following, arguably serving as indications of 4x hyperthreading. Your thoughts(?), thanks.

1. Please see the following excerpt in https://en.wikipedia.org/wiki/Xeon_Phi under heading Knights Corner->Design and Programming.
   • "Design elements inherited from the Larrabee project include x86 ISA, 4-way SMT per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per core[56]), and ultra-wide ring bus connecting processors and memory."
2. Also, please see below results followed by source code provided by a colleague indicating support for 240 threads on each of 2 Xeon Phi (7120p not shown) coprocessors hosted on one of our campus cluster's compute nodes, an Intel(R) Xeon(R) CPU E5-2680 v2. 

<begin results>

Number of platforms : 1
Platform 0:
Name : Intel(R) OpenCL
Vender : Intel(R) Corporation
Version : OpenCL 1.2 LINUX
Number of devices : 3
Device 0:
Name : Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz
Max Compute Unit : 20
Max Work Group Size : 8192
Device Native Vector Size of Float : 8
Device Native Vector Size of Double : 4
Device Main Memory Size : 3173060608
Device 1:
Name : Intel(R) Many Integrated Core Acceleration Card
Max Compute Unit : 240
Max Work Group Size : 8192
Device Native Vector Size of Float : 16
Device Native Vector Size of Double : 8
Device Main Memory Size : 3610112000
Device 2:
Name : Intel(R) Many Integrated Core Acceleration Card
Max Compute Unit : 240
Max Work Group Size : 8192
Device Native Vector Size of Float : 16
Device Native Vector Size of Double : 8
Device Main Memory Size : 3610112000

<end results>

<begin source>

#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <numeric>
#include <sys/time.h>

#ifdef __APPLE__
#include <OpenCL/opencl.h>
#else
#define CL_USE_DEPRECATED_OPENCL_2_0_APIS
#include <CL/cl.h>
#endif

#define MAX_PLATFORM_IDS 8 //max platform_id
#define BUFFER_SIZE 4096 //information buffer size
#define MAX_DEVICE_IDS 8 //max devices

int main(int argc, char **argv) {
cl_uint status;
cl_platform_id platform_ids[MAX_PLATFORM_IDS];
cl_uint num_platforms;
status = clGetPlatformIDs(MAX_PLATFORM_IDS, platform_ids, &num_platforms);
std::cout << "Number of platforms : " << num_platforms << std::endl;

for (cl_uint pid = 0; pid < num_platforms; pid++) {
char param_value[BUFFER_SIZE];
size_t param_value_size_ret;
std::cout << "Platform " << pid << ":\n";
status = clGetPlatformInfo(platform_ids[pid], CL_PLATFORM_NAME,
BUFFER_SIZE, param_value, &param_value_size_ret);
std::cout << "Name : " << param_value << std::endl;
status = clGetPlatformInfo(platform_ids[pid], CL_PLATFORM_VENDOR,
BUFFER_SIZE, param_value, &param_value_size_ret);
std::cout << "Vender : " << param_value << std::endl;
status = clGetPlatformInfo(platform_ids[pid], CL_PLATFORM_VERSION,
BUFFER_SIZE, param_value, &param_value_size_ret);
std::cout << "Version : " << param_value << std::endl;
cl_device_id device_id[MAX_DEVICE_IDS];
cl_uint num_devices;
status = clGetDeviceIDs(platform_ids[pid], CL_DEVICE_TYPE_ALL,
MAX_DEVICE_IDS, device_id, &num_devices);
std::cout << "Number of devices : " << num_devices << std::endl;
for (cl_uint did = 0; did < num_devices; did++) {
std::cout << "Device " << did << ":\n";
clGetDeviceInfo(device_id[did], CL_DEVICE_NAME, BUFFER_SIZE,
param_value, &param_value_size_ret);
std::cout << "Name : " << param_value << std::endl;
clGetDeviceInfo(device_id[did], CL_DEVICE_MAX_COMPUTE_UNITS,
BUFFER_SIZE, param_value, &param_value_size_ret);
std::cout << "Max Compute Unit : " << *(cl_uint *) param_value
<< std::endl;
clGetDeviceInfo(device_id[did], CL_DEVICE_MAX_WORK_GROUP_SIZE,
BUFFER_SIZE, param_value, &param_value_size_ret);
std::cout << "Max Work Group Size : " << *(size_t *) param_value
<< std::endl;
clGetDeviceInfo(device_id[did], CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT,
BUFFER_SIZE, param_value, &param_value_size_ret);
std::cout << "Device Native Vector Size of Float : "
<< *(cl_uint *) param_value << std::endl;
clGetDeviceInfo(device_id[did],
CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE, BUFFER_SIZE,
param_value, &param_value_size_ret);
std::cout << "Device Native Vector Size of Double : "
<< *(cl_ulong *) param_value << std::endl;
clGetDeviceInfo(device_id[did],
CL_DEVICE_GLOBAL_MEM_SIZE, BUFFER_SIZE,
param_value, &param_value_size_ret);
std::cout << "Device Main Memory Size : "
<< *(cl_uint *) param_value << std::endl;
}
}

return 0;
}

<end source>

Best,

CB

[JoseH_Intel]

Hello cb4letni,

Thanks for sharing this information. Take into consideration that wikipedia is not an Intel official information source so we cannot validate or deny what is been said there.  Let me research further on this and I will let you know as soon as I have any updates. 

Regards

Jose A.

Intel Customer Support

[haiqu]

cb4letni: The 7120 has 61 cores and 244 threads. It therefore supports hyperthreaading.

[JJK]

well, yes and no.

The 7120P has 61 cores and 241 threads but those are NOT hyperthreads.  The Xeon Phi (KNC and KNL) have 4 threads per core, period. A hyperthread is like "half" an extra core on a regular Xeon/Intel processor and you can (& should, most of the times) turn off hyperthreading when doing floating point intensive tasks.

On the KNC you can not even turn off the other threads without causing the card to get stuck in an unstable state.