100 Ohm resistor with LVDS receiver

[Altera_Forum]

Hi, 

 I am intending to interface ADS5282EVM with Altera DE2 115 Development board via HSMC connector.   Referring to the DE2_115_User_manual_2013, page# 41;  additionally, when lvds is used as the i/o standard of the hsmc connector, the lvds receivers need to assemble a 100 ohm resistor between two input signals for each pairs.  Do I need to assemble an additional 100 Ohm resistor myself ? I am sampling at 20 MHz, is it really necessary to attach it ?  Thanks for your help.

[Altera_Forum]

--- Quote Start ---   Do I need to assemble an additional 100 Ohm resistor myself ? I am sampling at 20 MHz, is it really necessary to attach it ?   --- Quote End ---   Yes, you need the 100-Ohm resistor. LVDS drivers output a current, and that current develops a voltage over the 100-Ohm resistor. Without the resistor the LVDS interface will not function.  I believe the DE115 board has locations on the PCB for the 100-Ohm termination resistors, but you need to solder them on. You also need to make sure that the I/O bank voltage is changed to 2.5V to be compatible with LVDS - telling Quarus that the bank VCCIO = 2.5V is not sufficient to change the voltage, you have to both change the constraint and physically change the voltage.  Cheers, Dave

[Altera_Forum]

Thanks for the useful information Dave. I really appreciate.

[Altera_Forum]

Hello. 

Related with this, please help me. Are all IO Banks dedicated LVDS receivers, not emulated? I am confused because IO banks 1, 2, 5 and 6 are the only dedicated TRANSMITTERS, does this applies to the RECEIVERS?  Best regards

[Altera_Forum]

--- Quote Start ---   Related with this, please help me. Are all IO Banks dedicated LVDS receivers, not emulated? I am confused because IO banks 1, 2, 5 and 6 are the only dedicated TRANSMITTERS, does this applies to the RECEIVERS?   --- Quote End ---   Which part are you talking about? Altera devices have dedicated LVDS transmitters and receivers containing serializer or deserializer hard-IP blocks. You can also emulate LVDS, but those pins run slower and do not have a SERDES option. The handbook for the device you are using has details.  Cheers, Dave

[Altera_Forum]

Hello Dave, thank you for your reply. 

I need to use 4 clock inputs. To use the 4 pll's. I have to confirm that the dedicated clock pins can be LVDS or not. I prefer to use dedicated input clock signals not emulated. In the documentation it is not clear that the LVDS input buffers are dedicated or not. The device (Cyclone III) documentation refers to dedicated lvds transmitters placed at 1, 2 5 and 6 IO Banks. The reason of my confusion is that in the same documentation (Cyclone III Device Handbook Volume 1 page 6-20) says and I quote "The LVDS standard does not require an input reference voltage, but it does require a 100-Ωtermination resistor between the two signals at the input buffer. An external resistor network is required on the transmitter side for top and bottom I/O banks." However in Cyclone III Device Handbook Volume 1 page 6-13 says in Note 8 of Table 6–4: "True differential LVDS, RSDS, and mini-LVDSI/O standards are supported in left and right I/O pins while emulated differential LVDS(LVDS_E_3R), RSDS(RSDS_E_3R), and mini-LVDS(LVDS_E_3R) I/O standards are supported in both left and right, and top and bottom I/O pins." So, do all the IO banks have dedicated LVDS receivers only requiring a 100-Ωtermination resistor or should I consider that dedicated LVDS I/O standards are ONLY supported in both left and right, and top and bottom I/O pins. This indicates if I need to change my board layout or not. Regards Miguel

[Altera_Forum]

--- Quote Start ---   I need to use 4 clock inputs. To use the 4 pll's.   --- Quote End ---   If the clock inputs on the part you are using (which you did not mention - Cyclone III with what part number?) have names like CLK1p and CLK1n, then that implies the clock input supports a differential clock. Many of the device handbooks support LVDS input on these clocks independent of the VCCIO bank voltage, since the differential receivers are powered from another supply. Go back through the handbook and *ignore* the LVDS transmitter and receiver details, and instead look at the clock descriptions. Chances are you missed the comments about LVDS input clocks (it might be in a footnote somewhere). If the device does not have on-chip termination support, you will need an external 100-ohm termination on your board.  Cheers, Dave

[Altera_Forum]

Sorry Dave. 

It's the EP3C55F780C6. You are right, I have been looking for LVDS receivers on the handbooks. Which turn into a big confusion to me. I decided to place a resistor in the layout but will not be placed. Let me search again on the documentation and I will turn back here. I saw you are a radio astronomer professional. I am working on a very high speed low cost correlator for radio astronomy.  Regards Miguel

[Altera_Forum]

--- Quote Start ---   It's the EP3C55F780C6. You are right, I have been looking for LVDS receivers on the handbooks. Which turn into a big confusion to me. I decided to place a resistor in the layout but will not be placed. Let me search again on the documentation and I will turn back here.   --- Quote End ---   If you cannot find the details, ask again, and I'll take a look.    --- Quote Start ---   I saw you are a radio astronomer professional. I am working on a very high speed low cost correlator for radio astronomy.   --- Quote End ---   "High-speed" is subjective, how high in MHz? I'm currently testing Hittite's 20GHz ADC for use in an expensive correlator system :)  Are you considering a polyphase filter bank solution? If so, I've done some testing with the Altera FFT you may be interested in ...  http://www.ovro.caltech.edu/~dwh/correlator/pdf/fft_tutorial.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/ee_live_14_hawkins.pdf  Cheers, Dave