100KHz 16bit PWM generation -- PLL manipulation?

[Altera_Forum]

I would like to replace my TI Picccolo with an FPGA. 

 The one major thing that the Piccolo has is the ability to generate a PWM signal with a resolution of 150 ps (yes, pico seconds), thus allowing me to have a base frequency of 100KHz and still get 16bit PWM generation.    150ps ~= effectively 6.6Ghz (FYI: The TI part actually does this in analog land)   I see that PLL manipulation (stx4_siv51005.pdf page 19) can get me approxomately 96pico second shifts.   Can I use this to generate my high resolution PWM signal to an external pin? And maybe it's inverse as well? Any Examples?

[Altera_Forum]

You should be able to fine-shift a pulse edge utilizing PLL dynamic phase shift capability, achieving the said resolution (1/8 of VCO period). As long as you don't need other high performance features, it should work also with Cyclone III. 

 Interesting points are intended update rate and number of parallel channels. I wonder however, if a fractional PWM modulator design can't achieve the same resolution with less effort?

[Altera_Forum]

I would like to be able to update the duty cycle every cycle (aka. every 10us, probably computing the error one or 2 cycles behind). Basically a PID loop would be reading in the next destination voltage for calculating the 'error', and stuff that resutiling PWM Duty Cycle into a 1 or 2 deep fifo. The negative edge of the PLL output would load in the next value into the phase shifter. That value would encode the width of the positive pulse. The beginning of that pulse would come from a 100khz clock. The duration of the pulse would be determined by the PLL/phase shifter. The PWM duty cycle would be limited to between 10% and 90%, to ensure that I have calcuated the next positive pulse width. 

 If I can do this with a $30 Cyclone III then it will only need to handle 3 of these PWMs per chip. (I will need 27 PWMs total per box, but using several FPGAs should be fine.....the master controller will probably be a Stratix or 2 that will be feeding the Cyclone's next value.)   What is a "fractional PWM modulator", the great google did not find that term (other than your post!)

[Altera_Forum]

I guess a better way to say it would be: 

a) The rising edge of a 100khz signal would peg the 'Set' of a flip-flop and start the Phase shifter.  b) The Phase shifter would then peg the 'Reset' of the flip-flop when the (high res) time has expired.   (I think....maybe?)

[Altera_Forum]

Fractional PWM modulator possibly isn't an unequivocal term. Fractional PLL or fractional clock divider in contrast is. The common idea is to achieve additional resolution by switching between two integer values in a defined pattern. An error accumulator makes the average value follow the ideal setpoint. If you can use fractional techniques without adding noticeable noise power within in the utilized signal spectrum depends on the available output filtering and partly on the algorithm to generate the modulation pattern. It can be e.g. a higher order sigma delta modulator. 

 Regarding PLL dynamical phase shift, you have to consider the restriction, that the PLL phase can be shifted only by single phase increment at PLL scanclk (100 MHz max.) speed. If dynamical phase shift is applied to multiple outputs of a PLL, the time budget has to be shared. The method seems to be fast enough to achieve a by-cycle setting for a 100 kHz PWM.

[Altera_Forum]

Just to check my understanding----- 

 Fractional PWM modulator -- So for a simple case, int1=XXX, int2=int1+yyy (where yyy=1) every other cycle gives you one extra bit of resolution.... change the range of yyy to 4 give you 2 extra bits, etc....with an associated increase in the appearant 'ripple'   "PLL dynamical phase shift ... only by single phase increment at PLL scanclk" -- this seems like an odd limitation, based on how fast the VCO can change I guess? -- anyway, so at the 100Khz Cycle by Cycle PWM this would mean that the maximum step change per PWM cycle would be 1000 (100Mhz/100khz), thus requiring 66 PWM cycles (2^16/1000) or 660 us to get from the max duty to the minimum duty.

[Altera_Forum]

To deal with "PLL dynamical phase shift ... only by single phase increment at PLL scanclk" It would make a lot more sense to deal with the first 10 Most Significant bits using the 100Mhz Clock (holding the Set in place) then use the 6 least significant bits to adjust the PLL.....thus I could go from 90% to 10% in one cycle.

[Altera_Forum]

Yes, you surely have to handle coarse and fine timing separately. The interesting problem is to keep an absolute timing reference for the phase shifted clock. I can't give you detailed suggestions, because I didn't use dynamic phase shift for the said purpose. But I'm convinced that it can work. Good luck!

[Altera_Forum]

Thanks, FvM!

[Altera_Forum]

Hi Eldenc, 

 I need to generate a 20Mhz PWM with some high resolution. I thing that your solution can help me do you have nay example or document about the implementation.   Thanks

[Altera_Forum]

sorry, we did not get much further than discussions on this project