Programmable Devices

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Programmable Devices

Discussions

driver request

uniphy DDR parameter reading from datasheet guide

Maximum avaliable frequency with the altera_gpio at Arria 10

MSEL wrong configuration

Timing closure for LVDS ADC input and related logic

How to reduce HUGE clock delays (Cyclone V)

License file

Altera DE1 cyclone ii send serial data to laptop via rs232

Simple DDR input in Cyclone V

software for flex 10k

Error Code: *** Fatal Error: Int Divide By Zero Module: quartus_map.exe Stack Trace:

Altium intlib of Cyclone IV GX and Arria V GX, whos has?

Cyclone V GX FPGA PLL not working

AN 641 design project

Boot and Configure Max10 FPGA from external serial flash?

Featured Content

Quartus Prime Design Software - JTAG usage

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

EPM3064ATC44-7N and EPM3064ATI44-10N

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage