10M16DCU324 external clock input voltage level

[XQSHEN]

hello,

The external clock was connected at FPGA bank2 clock input pin.

It will be used as PLL input, and then distribute clock to all FPGA banks.

1) clock input voltage is 1.8V at bank 2.

2) the voltage level of IO at bank4 is 3.3V.

The clock was routed from PLL will be used for bank4.

Is there any problem ?

[Ash_R_Intel · Accepted solution]

Hi,

Clock generated by an internal PLL can be routed to entire FPGA using global clock buffers. No bank voltage dependency.

Regards

[Ash_R_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you