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14703 MAX 10 Error

poming
New Contributor I
482 Views

I put Ethercat IP (license from Beckhoff) on MAX10 (10M25DAF484C8G) .

When I use quartus 18.1 compile the project, at Assembler stage, show 14703 at message console.

I can not modify any Ethercat IP source code, because it is black box.

What can I do to eliminate all these 14703 errors ? 

Thank you.

 

 

0 Kudos
10 Replies
AR_A_Intel
Employee
463 Views

Hi

 

Welcome to Intel forum. For further checking could you provide

1) License.dat file

2) OS version use

3) assembler report .asm.rpt file

•           The assembler report is located in <Project directory>/Output_files/<project_name>.asm.rpt.

 

And for privacy, you can reply/attach your file in private message.


poming
New Contributor I
456 Views

Hi AR_A_Intel,

I copy my Assembler report and Flow report as follows.

Please help to see if any clues.

Thank you.

 

Assembler report for A2E
Wed Sep 28 10:05:22 2022
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Encrypted IP Cores Summary
5. Assembler Messages

 

----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.

 

+-----------------------------------------------------------+
; Assembler Summary ;
+-----------------------+-----------------------------------+
; Assembler Status ; Failed - Wed Sep 28 10:05:22 2022 ;
; Revision Name ; A2E ;
; Top-level Entity Name ; A2E ;
; Family ; MAX 10 ;
; Device ; 10M25DAF484C8G ;
+-----------------------+-----------------------------------+


+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+


+---------------------------------------------------------+
; Assembler Encrypted IP Cores Summary ;
+----------+-------------------------------+--------------+
; Vendor ; IP Core Name ; License Type ;
+----------+-------------------------------+--------------+
; Beckhoff ; ETHERCAT (745C 1810) ; Licensed ;
; Beckhoff ; EtherCAT_VendorID (745C 1810) ; Licensed ;
+----------+-------------------------------+--------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition
Info: Processing started: Wed Sep 28 10:05:19 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A2E -c A2E
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error (14703): Invalid internal configuration mode for design with memory initialization
Error: Quartus Prime Assembler was unsuccessful. 60 errors, 1 warning
Error: Peak virtual memory: 4760 megabytes
Error: Processing ended: Wed Sep 28 10:05:22 2022
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:03

 

Flow report for A2E
Wed Sep 28 10:05:22 2022
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages

 

----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.

 

+--------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-------------------------------------------------+
; Flow Status ; Assembler Failed - Wed Sep 28 10:05:22 2022 ;
; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Standard Edition ;
; Revision Name ; A2E ;
; Top-level Entity Name ; A2E ;
; Family ; MAX 10 ;
; Device ; 10M25DAF484C8G ;
; Timing Models ; Final ;
; Total logic elements ; 14,856 / 24,960 ( 60 % ) ;
; Total combinational functions ; 12,074 / 24,960 ( 48 % ) ;
; Dedicated logic registers ; 8,055 / 24,960 ( 32 % ) ;
; Total registers ; 8055 ;
; Total pins ; 131 / 360 ( 36 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 491,536 / 691,200 ( 71 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 110 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 2 ( 0 % ) ;
+------------------------------------+-------------------------------------------------+


+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/28/2022 10:02:23 ;
; Main task ; Compilation ;
; Revision Name ; A2E ;
+-------------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 66325072577943.166433054310136 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; EpLL_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; EpLL.ppf ; -- ; -- ; -- ;
; MISC_FILE ; EEpLL_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; EEpLL.ppf ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:01:36 ; 1.0 ; 5000 MB ; 00:01:46 ;
; Fitter ; 00:01:14 ; 1.4 ; 5916 MB ; 00:02:22 ;
; Assembler ; 00:00:03 ; 1.0 ; 4760 MB ; 00:00:03 ;
; Total ; 00:02:53 ; -- ; -- ; 00:04:11 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+


+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; TWTN1PC1005 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; TWTN1PC1005 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; TWTN1PC1005 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off A2E -c A2E
quartus_fit --read_settings_files=off --write_settings_files=off A2E -c A2E
quartus_asm --read_settings_files=off --write_settings_files=off A2E -c A2E

AR_A_Intel
Employee
452 Views

Hi

 

Thanks for update. could you help try the solution in KDB link below https://www.intel.com/content/www/us/en/support/programmable/articles/000074796.html

You may test it see how things go.

Report back if error happen with error message screenshot.


poming
New Contributor I
451 Views

Hi AR_A_Intel,

I have told that I can not modify any Ethercat IP source code, because it is Encrypted IP.

The Encrypted IP use RAM, but I can not read the code, I can not modify the code.

Do your know that any setting within QuartusII for me to set  to solve this issue ?

Thank you.

Farabi
Employee
440 Views

Hello,


Please change the code in RAM/FIFO block (not in the ethercat block):


Resolution:

--------------

Signal declaration for memory_type should be changed from


  signal mem : memory_type :=(others => (others => '0'));


to


  signal mem : memory_type;


regards,

Farabi


poming
New Contributor I
415 Views

Hi Farabi,

The memory (RAM/FIFO) used inside Ethercat encrypted IP block.

I can not touch the code.

So, if you have any setting in Quartus to solve this issue.

Thnaks !

AR_A_Intel
Employee
392 Views

The signal declaration is usually in the RTL of customer’s memory design module / top level module. This is where the change needs to be done.


poming
New Contributor I
389 Views

Hi,AR_A_Intel,

I think you have done your best though it is not helpful for me.
thank you.

Farabi
Employee
374 Views

Hello,


Can you provide us your simple design for us to replicate at our end?

This will speed up the debugging work.


I will contact you through email.


regards,

Farabi


AR_A_Intel
Employee
226 Views

We do not receive any response from you to the previous reply that we have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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