Greetings Altera Forum! I've got some problems that's been bugging me for quite some time now. I can't find the answer (or I lack googling skills).Question 1: How can I use a keyboard as a mean to input something for the FPGA Board? Also, how many bits is the input and how is the input represented? I'm guessing it is an 8-bit ASCII. Question 2: How to use TCL file for VHDL?I only used a TCL file for synthesizing Verilog codes using set_location_assignment PIN_### -to NAME[arrayIndex]. It works flawlessly, but now I tried it using a VHDL file replacing the square bracket  with circular () and it does not return any error. However, it also does not work. I tried using a simple LEDG <= "10101010" but the result is was, not a single LED lights up. My next attempt is to import the QSF file so that all pins are ready to use, but I still haven't tested that yet if it will work (because the FPGA board is only available on school days). Any help will be appreciated, thanks.
Many development boards include PS2 connectors for keyboards. See the schematics for information on safely hooking a PS2 port to an FPGA. There are multiple references on the internet on the protocol used for PS2 keyboards. Also, these same boards usually include example projects using the PS2 port.I've never used VHDL attributes for pin assignments. Are these even supported by the Altera tools? I'd recommend that you stick with standard I/O constraints.
Hi thanks!As for question1, I did some research on PS2 keyboard as input for FPGA and found an answer. Seems like keyboards use a Make and Break Code whose number of bits depends on the button pressed (Arrow keys has more). Anyway, question 1 is solved. Thanks for suggesting PS2 keyboards. Sorry for the noob question, stuffs like these are the things that anyone can figure out on their own. I should have done more research before asking. As for question2, I saw some youtube videos using VHDL as the HDL for Altera Cyclone II DE1 Board and it works fine. I couldn't find any reason why it would not be supported because VHDL is one of the major HDL What's the standard I/O constraints? Can you give an example? Thanks in advance (+rep)
You need to do more research. You can find a description of I/O constraints in the Quartus documentation. Go to the Altera website and click the Documentation link. Then click Quartus Prime Software under the Software and IP heading. The I/O constraints are covered in chapters 1 and 2 of volume 2 in the quartus handbook. There is also an introduction that has a good overview of the development process.I prefer to use the pin planner, but sdc files are also popular. Most dev boards come with project examples that have already specified the I/O constraints. It's probably best to use one of these as a starting point. It is possible to damage the FPGA if voltage I/O constraints aren't correct. Also, some settings needed for high speed make the FPGA more subject to ESD. It's a good policy to always reuse constraints from a working project.