Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

3.3V Single end IO Logic support for Stratix4 GX

Altera_Forum
Honored Contributor II
‎02-29-2012 12:26 PM
1,340 Views

Hi, 

We are using EP4SGX70 device. As per DC and Switching Characteristics datasheet, EP4SGX70 dosent support 3.3V IO logic. But it says it can support 3.3V input. 

Dose that mean that I can use 3.0V IO bank for connecting 3.3V device interfaec? 

Is it recommended to use 3.3V device interfaec with EP4SGX70? 

 

Regards, 

Sachin.M.K
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎02-29-2012 05:07 PM
453 Views

Stratix IV I/O buffers support 3.3-V I/O standards. You can use them as transmitters 

or receivers in your system. 

 

http://www.altera.com/literature/hb/stratix-iv/stx4_siv51006.pdf
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎03-01-2012 04:51 AM
453 Views

Thank you.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.