4-QAM output error

[Altera_Forum]

Hi, 

 I am trying to build a 4-QAM on an Altera FPGA and am having problems with the simulation on ModelSim.   Attached to this thread is my code "qam4.vhd" which is the 4-QAM code and "testbench_qam4.vhd" which is the testbench for the code.  Can someone tell me why am i getting the results as I am getting in ModelSim as attached in the file "QAM_ModelSim_error.jpg". the real output and imag output don't seem to match what I coded in the file "qam4.vhd".  The input data is extracted from the file "data.txt"  Thank you so much, any help will be much appreciated.

[Altera_Forum]

You migth just say: 

if input = "00" then real <= "11"; -- -1  imag <= "01"; -- +1 elsif input = "01" then...

[Altera_Forum]

Thanks Kaz for the reply and help, but somehow, I am still getting errors in the results =( as attached in the file " QAM4_ModelSim_error_21_04_2011.jpg" 

 I noticed that my output takes up 2 clock cycles each, which I don't understand why this is happening.  Will you help me to look through the file? I am pretty new to VHDL and I really want to solve this problem. Attach is the file amended as you recommended. Thanks again, really appreciate your help.

[Altera_Forum]

By my initial post I meant you don't need any extra code apart from mapping input bits to output directly. You don't need buffer or enable. just straightforward mapping.

[Altera_Forum]

Thank you so much Kaz, I finally got it working. Simplicity as you suggested, was the way to go. =)