40 Gbps QSFP arria 10 analog parameters

[empissas]

Hi ,

I am working on a custom  implementation that is based on the Transceiver PHY IP core. We use the  TR10a-LPQ development board. In our design  we connected  via an Optical QSFP+ Cable  the two QSFP+ connectors.  We used the enhanced protocol with 10Gbps data rate. Although  the data that are retrieved between the TX and RX channel  are not valid . I  assume  that we have to set  the appropriate values on  the  transceiver analog parameter settings  related to :

  Receiver :

- Receiver On-Chip-Termination
- Receiver Link Type
-VCCR_GXB/VCCT_GXB Voltage
-Receiver High Data Rate Mode Equalizer
-Receiver High Gain Mode Equalizer DC Gain Control
-Receiver High Gain Mode Equalizer AC Gain Control
-Receiver Variable Gain Amplifier Voltage Swing Select
-and if we have to use the Decision feedback
equalization (DFE) or not

Transmitter:

-Transmitter Link Type
-Transmitter On-Chip Termination
-Transmitter High-Speed.Compensation
-VCCR_GXB/VCCT_GXB Voltage
-Transmitter Slew Rate Control
-Transmitter Pre-Emphasis First/Second Pre-/Post Tap Polarity
-Transmitter Pre-Emphasis First/Second Pre-/Post Tap Magnitude

We have tried variable combinations based on the documentation of the ip core but we haven't achieved to retrieve valid data.

Did anybody face this problem   before or   managed to implement a 10Gbps link  with specific analog parameter settings ?

Thanks 

[Deshi_Intel · Accepted solution]

Hi,

Transceiver PMA analog parameter link tuning process is very dependent on the board design.

• Different board may required to use different PMA setting

For Intel FPGA side, our Arria 10 "low latency 40G Ethernet IP" example design is verified using "Arria 10 GX Transceiver Signal Integrity Development Kit"

• You can find out more about the example design in below link but as I said the PMA setting may not be suitable to you since you are using different board
• https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/deug_ll_40ge.pdf

I can see that you are using Terasic TR10a-LP dev kit board, then my suggestion is why not you consult Terasic directly.

• Ask them how they validate 40G Eth transaction on their board ?
• Is there any 40G Eth reference design that can share with you ?
• You can try reach out to Terasic via support@terasic.com

Thanks.

Regards,

dlim