Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,109 Views

5.8GHz PLL output from Cyclone V?

From an early look at Cyclone V documentation it appears that a PLL could be configured for an output of 5.775GHz. Is this correct? Can the output be ported to a differential output of the chip?

0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
46 Views

Hi, 

 

Not supported. 

Cyclone V supports PLL input clock range of 5MHz to 670MHz. 

https://www.altera.com/en_us/pdfs/li...v/cv_51002.pdf 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

Hi, 

 

Not supported. 

Cyclone V supports PLL input clock range of 5MHz to 670MHz. 

https://www.altera.com/en_us/pdfs/li...v/cv_51002.pdf 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

 

Thanks, Anand. Sorry for the confusion. My real question is about the output frequency of the PLL. Can it go up to 5.775 GHz, and can it be pumped out of the chip on a differential output like LVDS? 

 

Regards, 

Glenn
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

Thanks, Anand. Sorry for the confusion. My real question is about the output frequency of the PLL. Can it go up to 5.775 GHz, and can it be pumped out of the chip on a differential output like LVDS? 

 

Regards, 

Glenn 

--- Quote End ---  

 

 

The document referenced indicates the maximum PLL Fout is 550MHz for internal clock tree, and 667MHz for external clock pin (table 30 pp.40-41). 

 

Where are you getting the 5.775GHz value from? I don't see that referenced anywhere. 

 

I'm guessing it could be the PLL internal VCO maximum frequency, but there is no direct access to that node. It goes thru the PLL output divider first, which divides it down to the 550-667MHz range.
Reply