5CEBA7F27C8N_Power Supply Pin connection

[ShivaKi]

Hello,

For 5CEBA7F27C8N FPGA part, required clarification on VREF[#]N0 pins connection.

For example, Bank 6A is operating at 2.5V and we have considered two I/O standards "2.5V LVDS" and "LVPECL" in Bank 6A.

Based on these two I/O standards considered in Bank 6A, do we need connect "VREFB6AN0" pin to VCCIO of 6A bank or can we connect it to ground? Please confirm

[FvM]

Hi,
VREF is only used for voltage referenced I/O-standards, SSTL and HSTL. Neither LVDS nor LVPECL need it. So GND connection of VREF is the standard option.
Regards
Frank

[AqidAyman_Intel]

Hello,

May I know if you need any more clarification after answers provided by Frank?

Regards,

Aqid