64-bit data width DDR2 SDRAM usage (problem with SOPC builder)

[Altera_Forum]

I am using the DDR2 SDRAM controller Megacore function in SOPC builder, and I cannot configure it with 64-bit data bus width (128 local width). The SOPC builder generates errors regarding address span overlap when generating the system, so I moved the native addressing components farther apart so that base addresses won't overlap. But the memory map cannot fit within addressable memory space of the Nios II Data Master which is restricted to 31 address bits. 

I am still stuck in here and cannot figure out what to do :confused:, so if anyone has an idea to solve this, i will be grateful.

[Altera_Forum]

Two things to remember: 

1 - Use "System->Auto Assign Base Addresses" to allow SoPC builder to automatically figure out address ranges for your components. 2 - You can't have more than 2GB of address space. So if your DDR2 component is bigger than 1GB, you're probably going to run out of address space.  Jake

[Altera_Forum]

The SOPC builder regards address spans for some components while generating the system, and some of these addresses cannot be archived since the memory map cannot fit within addressable memory space of the Nios II Data Master which is restricted to 31 address bits. 

So I am afraid that won't work out!

[Altera_Forum]

Pick a smaller DDR device?

[Altera_Forum]

I think I need the entire bus to increase the performance