93% usage, ripple clocks warning

[Altera_Forum]

The outputs are doing what I want them to, but I'm getting warnings about ripple clocks, etc. 

 The compiler says 93% usage (60/64 cells).  Would like to stick with the lower cost 44 pin device.  Warnings come from an edge detector used to create a trigger pulse.  The registered "signal" clocks a DFF (D=1), Q loads a counter, then overflow resets the DFF. Q is the resulting trigger pulse.  For the counter, I used a 74161. I added two cascaded TFF's to give me a total pulse width of 64 clocks.  I searched and saw a post about using FF enables to do this, but don't understand.  This is for an engine timing controller. Eight inputs, eight outputs, plus a couple of signals to and from a uP.  One degree of timing at 10,000 RPM is 16.6 usec. Don't see a need for a clock faster than 1Mhz. Can I ignore the warnings, or do I need to go to the next bigger device and fix it?

[Altera_Forum]

I registered the reset pulse after my counter chain and that fixed one of the warnings. 

 For the other warning, I swapped in a DFFE for DFF, but now I get negative slack times for clock hold.  In the DFF version, a signal is used to clock a DFF (D=1), Q enables a counter, which (registered) resets the DFF at overflow. Q is high for 64 clocks. Clock hold slack times are 5ns.  For the DFFE version, a signal feeds DFFE enable, clk to clk in, D=1, but this causes clock hold slack times to be negative.

[Altera_Forum]

It sounds more like a warning for the way you solved your task. You could read -> Quartus II Handbook Volume 1: Design and Synthesis -> Section II. Design Guidelines -> Chapter 5. Design Recommendations for Altera Devices and the Quartus II Design Assistant (especially "Design Guidelines") and maybe there is a usefull suggestion which would fix the warning.