A Question about Operating DDR3 IP with UNIPHY.

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

A Question about Operating DDR3 IP with UNIPHY.

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Hi!

The interface between user and IP is Avalon-MM, I have known some operations of timing using this Interface.

My question is, my project instantiates a DDR3 IP, when I begin to do some read or write in the continous addresses, how can I determine the address increasing step length.

like when I write data in the address1, how comes the next address2 = address1 + ?.

For example, my ddr3 core, 128M16, the address format is like [CHIP-ROW-BANK-COL](1-14-3-10), the data width is 16; and in avalon-MM port, I set the data width is 64.

The avl-address is 26 bit width, not (14+3+10=)27? In my simulation, I found the address increment is 16, why is that?

Thanks in advance!

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