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VGolo1
Beginner
202 Views

A problem with Cyclone/Arria 10GX Transciever

Hello everyone! I need help!

I have two modules based on Arria 10GX (10AX066H4F34E3SG) and Cyclone 10GX (10CX220YF780I5G). The task is to make a 1G fiber Ethernet (1000Base-X) using GX functions of any of these modules (doesn’t matter which one). I’ve made projects using a Triple Speed Ethernet component, atx_pll and PHY Reset controller. Input frequency is 125 MHz and atx_pll makes 1250 Mhz for a TSE component. 100 Mhz is connected on a CLK_USR pin and I don’t use it in the project. Both projects keep silent on TX and they don’t see any receive signal but using oscilloscope I can see an RX fiber signal and nothing on TX pin on the path to SFP. I tried to make a fiber loop, then I tried to connect to a fiber switch but modules don’t see any receiving or transmitting signal. Maybe I should use Native PHY? Or did I provide wrong frequency? Does TSE use a LOS signal? I’ll appreciate if someone provides me with some 1G GX example or advice. Schemes and project are attached.

GX_OPTO: R3, R6, R7-R14 are removed. 0 Ohm resistors are installed instead of C2, C3, R4-R5, R1-R2 (direct connection).

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5 Replies
Deshi_Intel
Moderator
75 Views

HI,

 

The best way to help you is to introduce TSE 1G example design to you as reference to cross check with your own design.

 

Thanks.

 

Regards,

dlim

VGolo1
Beginner
75 Views

Thank you for your answer but this project is based on Marvell 88E1111 chip and I need a direct connection between FPGA and SFP. Moreover, the project uses LVDS I/O instead of GX functions. My PCB uses GX functions and pins. Should I use TSE or Native PHY and can you give me any applicable example?

Deshi_Intel
Moderator
75 Views

HI,

 

I see. Unfortunately our TSE IP reference design is based on what I shared with you using LVDS IO.

 

On the other hand, NativePHY IP itself is just a skeleton IP where we freely allow customer to build any custom protocol solution on top of it. There won't be any reference design on it as reference design is developed to target certain application protocol.

 

For your case, the more appropriate reference design for you will be Ethernet PHY IP that can run on 1G.

 

You can checkout below LL Ethernet 10G MAC IP where you can customize the setting to generate Ethernet MAC + PHY example design that support 1G application.

 

Thanks.

 

Regards,

dlim

 

 

Deshi_Intel
Moderator
75 Views

Below is the link to list of Ethernet IP solution offered by Intel FPGA but I can't promise you we have reference design ready for all these IP.

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
75 Views

HI,

 

I don't hear back from you after my feedback.

 

Hopefully you are doing well with your project development

 

For now, I am setting this case to closure.

 

Thanks.

 

Regards,

dlim

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