A question about cyclone iv ddr2 pin assignment

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

A question about cyclone iv ddr2 pin assignment

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Hi,

I have a question about cyclone iv ddr2 pin assignment.

There is a rule about ssn that no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in.The OUTPUT_ENABLE_GROUP assignment could bypass the rule above.

My question is that if using OUTPUT_ENABLE_GROUP assignment,and the design finally includes more than 9 output/bidirectional pins within 12 consecutive pads, is there something unstable or questionable for fpga?

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