- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hi,
SoC Booting happening though SDcard with early IO release configuration.
Is there any limitation for the early IO release configuration as i am facing this issue after adding HIP pcie rootport along with EMIF and a HIP PCIe Endpoint.
can somebody please put some light on this topic!!
valuable suggestions are most welcome.
following is the log .
........................................................................................................................................
U-Boot 2014.10-00328-g2a2102e-dirty (Sep 22 2017 - 13:32:45)
CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
FPGA: writing ghrd_10as066n2.periph.rbf ...
FPGA: Early Release Succeeded.
DDRCAL: Success
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe386e8
DRAM : 1 GiB
WARNING: Caches not enabled
MMC: *** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Model: SOCFPGA Arria10 Dev Kit
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net: dwmac.ff800000
Error: dwmac.ff800000 address not set.
Hit any key to stop autoboot: 5 4 3 2 1 0
FPGA: writing ghrd_10as066n2.core.rbf ...
Full Configuration Succeeded.
** Unable to read file u-boot.scr **
4377664 bytes read in 204 ms (20.5 MiB/s)
26597 bytes read in 10 ms (2.5 MiB/s)
FPGA BRIDGES: enable
Fail: noc_idleack = 0x00110000 mask_noc = 0x01010111
Kernel image @ 0x008000 [ 0x000000 - 0x42cc40 ]
## Flattened Device Tree blob at 00000100
Booting using the fdt blob at 0x000100
Loading Device Tree to 01ff6000, end 01fff7e4 ... OK
Starting kernel ...
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
Please refer the document below
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-fpga-early-io-release.pdf
The section 4. Debugging Early I/O Release
mentions about the debugging steps which can be followed to troubleshoot the early io release issue,
Please let us know after you tries out the same, and any other observation which comes along.
Thanks and Regads
Anil
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
thanks for the reply,
will check it..!!
as the FPGA is configured and the boot of HPS is stuck at uboot , i think the issue is something else..!!!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Similar issues are also observed due to Device Tree mismatches between the custom board and reference design.
Please see the links below
https://forum.rocketboards.org/t/arria-10-unable-to-mount-rootfs/2202/7
https://forums.intel.com/s/question/0D50P00003yyS4cSAE/stuck-at-starting-kernel?language=en_US
https://forums.intel.com/s/question/0D50P00003yyMhgSAE/help-my-kernal-is-panic-and-he-is-trying-to-kill-someone?language=en_US
Thanks and Regards
Anil

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page