I'm able to dinamically change the phase of an output clock of a PLL, but I have timinig issues on the input reset of the PLL. In particular, Quartus highlights a relation with negative setup slack between the PLL reference clock (FPGA input clock) and the clock used for the shifting interface that is one of the outputs of the PLL (but not the one that is shifted). I also tried to use the reference clock for the shifting interface, but the timing issues are still present. I didn't have an external reset, so I generated it with a counter that counts until a predefined value with the PLL reference clock. Is there a different and better way to internally generate this reset?
Hello, I am not sure about the timing issue you talking about, but about the reset can you use the PLL lock as the reset signal for the internal logic ?
Note : as along as input clock is stable Lock output will be stable .
Can i know why you looking for the reset signal ? i mean any specific reason ?
Thank you ,
Hi Sree, thank you for the answer.
I have already generated the resets for the internal logic from the PLL lock signal, one for each clock domain. The timing issue is related to the input reset of the PLL. In other projects, I generated the input reset of the PLL with a counter (as described in my question) and there were no timing issues. The only difference here is the Dynamic Phase Shifting interface and indeed the timing issue is on the PLL input reset signal from the PLL reference clock domain to the Dynamic Phase Shifting interface clock domain.
I probably didn't explain myself clearly. I was wondering if I have correctly generated the input reset of the PLL or if there are better ways to generate it, because in my project the timing requirement are not met for the input reset signal of the PLL.
I generated the PLL input reset with a counter that counts with the PLL reference clock. Instead, as you said too, I have generated the reset for the internal logic from the PLL lock signal. However, I had timing problems on the input reset signal. In particular, I used a PLL with the dynamic shifting interface activated. The timing violations is on the PLL input reset signal between the PLL reference clock domain and the one of clock used for the shifting interface.
I have never had a timing violation on the input reset of the PLL so I was wondering if I'm doing something wrong generating the input reset of the PLL in that way.
Hello Dario ,
Can i know input reset signal is asyn or syn with the clk ? I thought it is asyn , in that case isnt it reset signal generated by you is flase path ?
Thank you ,