AC/DC coupled LVDS on REFCLK

[Altera_Forum]

The Cyclone IV requires external termination if using AC coupled LVDS to the REFCLK pins. I have a couple of questions: 

 1- If the Vcm of the clock generator is compatible with the Vcm required by the REFCLK pins, can I DC couple the LVDS diff pair and just add a 100 ohm termination between the REFCLK pins?  2- If I do use AC coupling, can I use VCCINT as the biasing voltage instead of the 2-resistor voltage divider? My concern here is noise injected back into VCCINT.  I wish they had added OCT to these pins - that would have made layout a lot easier.  Thank you!

[Altera_Forum]

Hello, 

 I haven't implemented any Cyclone IV on a board (Only CI, CII, StxIII and StxIV up to now, using their LVDS and/or XCVR feature) but I would say:   1- To work properly, the inputs of a differential line receiver (clock or data) basically need to be properly biased and to see sufficient differential swing. In other words, the input differential signal Vcm and Vd must within the specified range for Vicm and Vid => So if your TX Vcm is within the RX Vcm range, the answer is YES you can DC-couple them.   2- I don't know whether the VCCINT value of Cyclone IV is compatible within the Vicm range nevertheless I would NOT recommend you to apply exactly the same biasing voltage to both inputs because this may lead the input buffer to oscillate when no signal is applied. A pair of 2-resistor divider (one for the positive input, the other for the negative input) should be preferred and calculated in order to have a small DC-offset between the two polarities (some tens of mV is enough). More over, you can add a decoupling capacitor located as close as possible to the upper resistors feed point to filter ripple from the biasing voltage. Don't worry about "noise injection": when properly designed, power planes offer very low impedance above DC which prevent other "clients" from being contaminated.   Generally, when your signal is a clock, I would rather recommend AC-coupling because the coupling capacitor acts as a DC-block but also as a high-pass filter that can attenuate any clock disturbator below the clock frequency. When your signal is a data, I would recommend DC-coupling as far as possible. This scheme allows for the straightest trace on the PCB layout which in turn is better especially for high data rates. Unfortunatly, the TX Vcm and the RX Vcm don't match most of the time, preventing DC-coupling from being implemented.   Oliver     PS: you are mentionning the "REFCLK" inputs which are part of the GXB blocks whereas LVDS TX and RX (True or Emulated LVDS) pins are located in different I/O banks. Though GXB and LVDS inputs are both differential, biasing and termination scheme do have some slight differences. Beware not to mix them.

[Altera_Forum]

Thank you for the reply Oliver! 

 AC coupling is the best solution, but as the layout stands, it makes it a little hard to add the 4 resistors needed for a proper termination. That is the reason I am looking at DC coupling.  The oscillator has the following LVDS output specs: Vcm = 1.2V Vod = 0.35 Vpp The Cyclone IV specs say that Vcm should be between 1.05V and 1.55V for that data rate I am using.  That sounds like I am within the specs, is that correct?

[Altera_Forum]

Apparently, the CycloneIV Vcm spec you are refering to is attached to some LVDS inputs located in column I/Os whereas in your initial post you were talking about a REFCLK input which belongs to a GXB block. 

 So, if your clock oscillator is connected to the input reference REFCLK0 or REFCLK1 of a transceiver block, Vicm spec is slightly different (and a bit ambiguous to be true...). Nevertheless, with a 1.2Vcm it will work as well.   If you are not using transceiver but true LVDS inputs, your clock source voltage levels are fully compliant so go ahead ! :-P

[Altera_Forum]

You are correct! The info on REFCLK is very confusing (as are other things with Cyclone IV). Altera had this on their support site: 

 http://mail.altera.com/support/kdb/solutions/rd06052012_702.html  This seems to mimic the LVDS data for regular LVDS inputs.  Thanks again for the help!