Hi all,I have a board with Cyclone V GX device in which i give the LVDS 2.5V clock from oscillator to Clk1p and Clk1n pins of FPGA. I have AC coupled the clock input and i have simulated the link in Mentor hyperlynx using Quartus generated LVDS input IBIS model with 100ohm Rd and oscillator IBIS model for LVDS2.5V. Simulation attached. Due to AC coupling, I was expecting that single ended signal on clk1p and clk1n pins at FPGA should have no DC bias but they are at VCM level of about 1.2V in simulation and even higher (around 2V) in oscilloscope measurements as this test board is already manufactured. My Question is : does lvds input buffer has internal dc bias which rises the ac coupled signal to 1-2v as i see in simulation and measurements ?
if yes, where can i find this info in the cyclone v documentation ? http://www.alteraforum.com/forum/attachment.php?attachmentid=10332&stc=1 Best regards waqas
--- Quote Start --- If yes, where can i find this info in the cyclone V documentation ? --- Quote End --- In the Cyclone V device datasheet https://www.alteraforum.com/forum/attachment.php?attachmentid=10333 Regards
Thanks genoli for your quick reply.I had read this information before too but i was not sure if it is more like a requirement for coming singal ended signal or it is a Cyclone V provided DC Bias. You mean that cyclone V provides 1.25VCM for all incoming LVDS P+ and N- signals ? Sorry but i just want to confirm if i am reading the documentation correctly. Thanks again.
Indeed, the 1.25Vcm voltage is the DC bias operating point of the LVDS buffer input stage which is not intended to "provide' any voltage to its outside world.Nevertheless, this is the voltage you will measure if you apply a voltmeter between GND and the input pins (p or n) as you've done and on every LVDS inputs. Consequently, you cannot apply any DC voltage at this input otherwise you will change the circuit operating point (hence, the buffer performance or functionality). If you implement DC coupling, your incoming signal shall not exceed the specified Vicm range. If you implement AC coupling, you don't have to care about that 'cause the blocking capacitor will prevent the output LVDS driver from disturbing the receiver input stage bias point It's the way it works for LVDS but for other differential logic standards with different Vcm as well (ECL, CML, ...). Have a good design !
Thanks alot.Now it is clear for me. Its just that Altera writes its documentation in quite confusing ways and then we have these kinds of support answers from then (http://wl.altera.com/support/kdb/solutions/rd01292014_586.html) which makes it even more confusing. But i can understand now what they want to say in their answers and documentation. conclusion is that Altera does provide the DC bias for incoming single ended signals by their input buffer operating point atleast in this case and device. I will start making detailed measurements soon and correlating them with simulations. I know what to expect atleast at the receiver pins. Thanks & Best regards waqas
The good thing with internal DC bias when you enabled the RD is it helps to save the on board resistor networks. You can opt not to use the RD and build your own biasing resistor network as well on the board when use AC coupling. If you are using DC coupling, then you need to ensure the VCM of your link meet the LVDS receiver VICM specs to ensure it can function as expected and avoid damaging the receiver.
I have the same question for the Cyclone 10 LP series: Does it provide internal DC bias for the LVDS inputs (since it doesn't have dedicated transceivers, I will use the GPIOs in LVDS mode)?I will connect it to a SGMII interface of a 1G Switch core, so I will need >700 Mbps data rates with AC coupling. For this speed the datasheet specifies a minimum common mode voltage (V_ICM) of 1.05 V. Should I need to add external resistor dividers for ~1.2 V DC biasing? Thanks for your help in advance.