AC coupling LVDS Tx - CML Rx

[Altera_Forum]

Hi, 

 I've read quite a few application notes here and there but have failed to come up with a solid conclusion. Whenever I've read on CML, it says they are mostly vendor specific so consult the data sheet. And Altera is not very helpful regarding CML, let alone PCML! I have tried to check the electrical specifications. But I'll be honest, I don't understand much of electronics :p  I have a DE3 (Stratix III) and a Stratix V DSP development kit. I want to connect 8 LVDS outputs from the DE3 to the 1.4V PCML inputs of the Stratix V DSP kit. DE3 http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=39&no=260&partno=2 Stratix V http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html  The hardware connections and terminations between the two confuse me. The maxim app note gives a schematic where only capacitors are connected in line with both wires.   Schematic on the last page.. http://pdfserv.maximintegrated.com/en/an/an291.pdf but no details..  TI gives an IC for this http://www.ti.com/product/sn65cml100  But I'm not sure if the IC can easily run for the 1.4V CML input on the Stratix V as it is compatible for 1.8,2.5 and 3.3V operations.  Also, putting 8 IC's could be tricky to route properly and maintain phase alignment.  I have talked around and have heard two 100nf capacitors in line will do. These days capacitors come in so many shapes and sizes and variations.  Could someone guide me in the right direction? Any help will be appreciated.   Thank-you.  Regards Zubair p.s. The links will run at around 1.5 Gbps.

[Altera_Forum]

AC coupling should work for all DC balanced (e.g. 8B/10B encoded) physical layer protocols, if the receiver supports it and is respectively configured. Small ceramic capacitors (0402 or 0603 size) are fine.

[Altera_Forum]

Thanks. 

 I understand the requirement for DC balance well and will make sure the data is encoded like that.  I overcame my fear of electronics and played around with LTspice a bit.  Square wave through a capacitor with a DC bias on the other side puts the square wave at the DC bias voltage on that side.  so basically. the DC biases are separate on both sides.  LVDS Tx has its own bias. 2.5V CML Rx has its own bias at. 1.4V  Connecting both sides with a capacitor will only allow the transition of a DC balanced signal across. And not the bias.  Vhigh-Vlow (differential signal) is similar for both LVDS and CML. Hence, connecting the two with a capacitor will work.  Now the question remains which part..  http://pdfserv.maximintegrated.com/en/an/an292.pdf helps a bit..  100nf ceramic capacitor. sizes 0402 and 0603.  http://www.digikey.com/product-detail/en/c1005x5r1a104k050ba/445-1265-1-nd/567732  Will this work?  Cheers Zubair

[Altera_Forum]

Small ceramic C's X5R or X7R are fine. Notihing to worry about.

[Altera_Forum]

Thank-you. 

 I am back with a slightly different question. A senior colleague informed me that input pins are not usually biased internally and, as I am AC coupling, I will have to DC bias my Stratix V CML input I/Os at 1.4V myself.  I tried looking at the Stratix V DSP kit schematic and couldn't find anything. And I checked the Stratix V device datasheet http://www.altera.com/literature/hb/stratix-v/stx5_53001.pdf without any luck at figuring out the answer to this problem..  Could anyone please shed some light on this?  Thanks  Cheers, Zubair

[Altera_Forum]

Found it in the Device transceiver handbook! 1-9, Page 19. 

 "Programmable VCM The receiver buffer has on-chip biasing circuitry to establish the required VCM at the receiver input."  Thanks  Cheers, Zubair

[Altera_Forum]

Yes. If a device supports a dedicated AC coupled IO-standard, it can be expected to have internal biasing. You'll need to apply external biasing for devices that are not prepared for AC coupled inputs, e.g. LVDS IO-standard.