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Altera_Forum
Honored Contributor I
1,691 Views

ADC Hard Block primitive

Hello, 

 

Does anyone know where the documentation/HDL instantitiation templates for the ADC Hard Block is located? I want to configure and access the ADC directly without using the modular adc IP. 

 

Thanks, 

- Sam
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12 Replies
Altera_Forum
Honored Contributor I
143 Views

Hi Sam, 

 

Yes can instantiate using macros. 

Not recommenced. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
143 Views

 

--- Quote Start ---  

Hi Sam, 

 

Yes can instantiate using macros. 

Not recommenced. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Really not very helpful! 

have you read through the documentation? 

https://www.altera.com/en_us/pdfs/literature/hb/max-10/ug_m10_adc.pdf
Altera_Forum
Honored Contributor I
143 Views

Hi Tricky, 

 

Let me know, if there is something wrong/missing anything. 

 

I have read that document, it explains "The Altera Modular ADC or Altera Modular Dual ADC IP core is a soft controller for the 

ADC hard IP blocks, we can generate soft IPs to instantiate the on-chip ADC blocks" 

 

But as per the question we need to instantiate the hard IP without using IP's. 

 

Using TCL/macros we can configure and instantiate it. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
143 Views

 

--- Quote Start ---  

Hi Tricky, 

 

Let me know, if there is something wrong/missing anything. 

 

I have read that document, it explains "The Altera Modular ADC or Altera Modular Dual ADC IP core is a soft controller for the 

ADC hard IP blocks, we can generate soft IPs to instantiate the on-chip ADC blocks" 

 

But as per the question we need to instantiate the hard IP without using IP's. 

 

Using TCL/macros we can configure and instantiate it. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Then why not show the OP how to do it?
Altera_Forum
Honored Contributor I
143 Views

I think the key line from the user guide is: 

 

--- Quote Start ---  

To create your ADC design, you must customize and generate the ALTPLL and Altera Modular ADC IP cores 

--- Quote End ---  

 

 

"must" is pretty clear to me. 

 

However if, using macros/tcl, there is a way of that suggests "must" actually means "don't have to", then I'd love to know how... 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
143 Views

Hi Tricky & Alex, 

 

Thanks For pointing at my mistake. 

 

Yes, it can't be done using macro. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
143 Views

Instantiating isn't really the problem... I dug through the output of the "megawizard" or whatever that thing is called. Here is how you instantiate it in VHDL: 

 

component fiftyfivenm_adcblock generic( -- 3-bits 1st stage clock divider. -- 0..5 = DIV by 1/2/10/20/40/80; -- 6..7 = invalid clkdiv : integer := 0; -- 2nd stage clock divider. -- 0 = DIV by 10; -- 1 = DIV by 20 tsclkdiv : integer := 0; -- 0 = Use 1st stage clock divider when TSEN. -- 1 = Use 2nd stage clock divider when TSEN. tsclksel : integer := 0; -- 2-bits To enable the R ladder for the prescalar input channels. -- 00 = disable prescalar for CH8 and CH16 (CH8 for device with 2nd ADC) -- 01 = enable prescalar for CH8 only -- 10 = enable prescalar for CH16 only (CH8 for device with 2nd ADC) -- 11 = enable prescalar for CH8 and CH16 (CH8 for device with 2nd ADC) -- please note that this is not supported in VR mode prescalar : std_logic_vector(1 downto 0) := "00"; -- Reference voltage selection for ADC. -- 0 = external; -- 1 = internal VCCADC_2P5 refsel : integer := 0; -- Ordering Part Number 10MXX... code device_partname_fivechar_prefix : string := "10M04"; -- Some part have two ADC, instantiate which ADC? 1st or 2nd? -- Valid options: 1 or 2 is_this_first_or_second_adc : integer := 1; -- 16 bits to indicate whether each of the dual purpose analog input pin (ADCIN) is in use or not. -- 1 bit to indicate whether dedicated analog input pin (ANAIN) is in use or not (bit 16) analog_input_pin_mask : integer := 0; -- Power Down. Use to disable the ADC during compilation time if no ADC is in use. hard_pwd : integer := 0; -- Logic simulation parameters which only affects simulation behavior enable_usr_sim : integer := 0; reference_voltage_sim : integer := 65536; simfilename_ch0 : string := "simfilename_ch0"; simfilename_ch1 : string := "simfilename_ch1"; simfilename_ch2 : string := "simfilename_ch2"; simfilename_ch3 : string := "simfilename_ch3"; simfilename_ch4 : string := "simfilename_ch4"; simfilename_ch5 : string := "simfilename_ch5"; simfilename_ch6 : string := "simfilename_ch6"; simfilename_ch7 : string := "simfilename_ch7"; simfilename_ch8 : string := "simfilename_ch8"; simfilename_ch9 : string := "simfilename_ch9"; simfilename_ch10 : string := "simfilename_ch10"; simfilename_ch11 : string := "simfilename_ch11"; simfilename_ch12 : string := "simfilename_ch12"; simfilename_ch13 : string := "simfilename_ch13"; simfilename_ch14 : string := "simfilename_ch14"; simfilename_ch15 : string := "simfilename_ch15"; simfilename_ch16 : string := "simfilename_ch16" ); port( chsel : in std_logic_vector(4 downto 0); -- 5-bits channel selection. soc : in std_logic; -- signal Start-of-Conversion to ADC eoc : out std_logic; -- signal end of conversion. Data can be latched on the positive edge of clk_dft after this signal becomes high. EOC becomes low at every positive edge of the clk_dft signal. dout : out std_logic_vector(11 downto 0); -- 12-bits DOUT valid after EOC rise, still valid at falling edge, but not before the next EOC rising edge usr_pwd : in std_logic; -- User Power Down during run time. 0 = Power Up; 1 = Power Down. tsen : in std_logic; -- 0 = Normal Mode; 1 = Temperature Sensing Mode. clk_dft : out std_logic; -- Output clock from the clock divider clkin_from_pll_c0 : in std_logic -- Clock source from PLL1 c-counter at BL corner or PLL3 c-counter at TL corner ); end component;  

 

I just want to find the documentation that explains the timing between EOC, SOC, DOUT, etc. I don't like to make comparisons but Xilinx has all their hard ip blocks well documented. Surely something similar must exist for Altera/Intel parts? 

 

I am rather concerned that "fiftyfivenm_adcblock" has 4 google results. 

 

The modular ADC is not an option for us seeing our design is going to be so tightly constrained by space limitations. The Modular ADC IP (even in it's smallest incarnation) is quite a bit larger than is needed.
Altera_Forum
Honored Contributor I
143 Views

Have you tried contacting Altera via mysupport? often, specific questions get you through directly to the correct support people, who can either provide the docs or tell you how to drive it.

Altera_Forum
Honored Contributor I
143 Views

Refer to figure 8 in the ADC Timing section of the "max® 10 analog to digital converter user guide (http://max® 10 analog to digital)". 

 

What you've instantiated there is essentially what results having configured the IP from the catalogue into 'Configuration 4: ADC Control Core Only'. Refer to section 2.2.1 "Altera Modular ADC IP Core Configuration Variants", in the same document. 

 

Cheers, 

Alex 

 

Edit 

**Sorry - need to acknowledge that's exactly what you said you did...
Altera_Forum
Honored Contributor I
143 Views

 

--- Quote Start ---  

Refer to figure 8 in the ADC Timing section of the "max® 10 analog to digital converter user guide (http://max® 10 analog to digital)". 

 

What you've instantiated there is essentially what results having configured the IP from the catalogue into 'Configuration 4: ADC Control Core Only'. Refer to section 2.2.1 "Altera Modular ADC IP Core Configuration Variants", in the same document. 

 

Cheers, 

Alex 

 

Edit 

**Sorry - need to acknowledge that's exactly what you said you did... 

--- Quote End ---  

 

 

No exactly... what I have instantiated is a very small part of that - altera_modular_adc_control.v 

 

Also included is a fifo, fsm, etc. I will take a look at those documents. Thanks.
Altera_Forum
Honored Contributor I
143 Views

 

--- Quote Start ---  

Have you tried contacting Altera via mysupport? often, specific questions get you through directly to the correct support people, who can either provide the docs or tell you how to drive it. 

--- Quote End ---  

 

 

I will try that. Thanks.
Altera_Forum
Honored Contributor I
143 Views

 

--- Quote Start ---  

Refer to figure 8 in the ADC Timing section of the <DELTED>. 

 

What you've instantiated there is essentially what results having configured the IP from the catalogue into 'Configuration 4: ADC Control Core Only'. Refer to section 2.2.1 "Altera Modular ADC IP Core Configuration Variants", in the same document. 

 

Cheers, 

Alex 

 

Edit 

**Sorry - need to acknowledge that's exactly what you said you did... 

--- Quote End ---  

 

 

For some reason I am having a hard time replying with a quote... 

This isn't exactly correct. ADC Control Core Only does implement a FSM and FIFO to support the Avalon-ST command/control interface. I am really looking for information on the raw control signals to the ADC block.
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