Hello,I'm a technician not a programmer. I would like to get some feedback from some of you experts. I have EP3C40 and EPCS16N using Active Serial and Quartus II. Sometimes the board configures and operates, then on another board it will still configure bit it won't operate correctly. The only thing I notice is I'm missing sclk signals, etc. required for some of the correct operations. I know it's vague, I'm looking for feedback and ideas that I can't come up with on my own. Thanks.
Hi Hondabones1.Do you mean DCLK? 2.Is timing constrains met? 3.Is both board having same design(schematic/board) Even board trace can add capacitance and introduce timing variations. 4.Check the operation after rest the design. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
1. sclk signal is a custom IO. These necessary signals are usually what's missing after it partially configures. The board is able to operate 90% off it's duties except where these clock signals are needed.2. We've had many successful boards already, I assume. I don't have a logic analyzer. The engineers, I believe, have thoroughly investigated this. 3. yes. all the boards are the same. In all of my research the circuit and trace design are correct. I'm going to ask the engineers if termination resistors are necessary for the serial configuration device where I connect the USB Blaster. It's my understanding if this is an issue then you are NOT able to configure. These boards are configuring, just partially. I've had many successful ones as well. 4. Do want me to allow the board to rest with power off for awhile? I don't understand your 4th point... sorry. Thanks for the response.
You might investigate whether the ability to configure or not is related to temperature or power supply variations. This could give you a clue as to what's going on.
--- Quote Start --- You might investigate whether the ability to configure or not is related to temperature or power supply variations. This could give you a clue as to what's going on. --- Quote End --- I guess I wouldn't say I can't configure. The Quartus II software says everything is green, however, I have all my signals and voltages etc. going in to the FPGA and some of the signals coming out are missing. I've already tried hardware repairs. It's a consensus that the FPGA is failing. I've had multiple boards come across my desk that work with no issues using the exact same .pof file. Unless there is a date code issue. I believe they've looked into power supply requirements. I just spent the last 2 hours checking heat. I may be on to something there, again though I've had countless success. Maybe my version of Quartus? Assuming there aren't any other issues. The problem seems to present itself randomly but it will affect 20 out of 25 boards. As a technician I'm not seeing issues on the board or from our manufacturing vendor. It's got the smartest of us stumped and those engineers are smart. I reached out on here to try and learn and understand from people like you. It may help me discover a board issue. Trying to remember what little I learned in college is nearly impossible. lol I had a semester of C that we put on an old 8051 microcontroller. Great ideas thank you.
Regardless of how you name your problem, I'd investigate temperature and power supply. This could point to a flaw in the logic design, or a design that's not constrained properly for timing. The chance that the "FPGA is failing" seems remote to me.
I'm pretty convinced your device is configuring successfully. Your suggestion that it's partial is understandable but not likely. Check the 'CONF_DONE' pin on the device if you're in any doubt. Assuming the design pulls this high with a resistor (as recommended in the design docs), it will go 'high' - to whatever voltage the resistor pulls it to - when the device is configured.I'm more concerned about a handling issue or excessive loads placed directly on FPGA pins configured as output signals, resulting in blown buffers on certain I/O pins. This I have seen on several device families including Cyclone III. I hope that latter (excessive loading) has been thoroughly considered and that the loading on 'sclk' is appropriate. I agree with gj_leeson too. You need to consider the power supply behaviour, particularly at power up. From the design docs for this family: --- Quote Start --- You can power up or power down the VCCIO, VCCA, and VCCINT pins in any sequence. The VCCIO, VCCA, and VCCINT must have monotonic rise to their steady state levels. The maximum power ramp rate for fast POR time is 3 ms, and 50 ms for standard POR time, respectively. The minimum power ramp rate is 50 μs. --- Quote End --- You particularly need to look for overshoot on any of these rails. These devices are not very tolerant, for very long, of much overshoot on certain rails. 'Monotonic rise' is also important. If something else on the board suddenly loads one of the FPGA rails part way through power up it'll affect the monotonicity of the rail's rise. I'd argue such a fault is a design issue so look to your design engineers if you find anything you don't like. Cheers, Alex
Yes. CONFIG_DONE goes high. I'm having them look into some of these suggestions. I also suggested enabling the pull-up resistors. Supposedly they are having issues with compiler. I was under the impression I had the same file as before. The date says I do. Thanks for the response.