hi...everyone.......
i am beginner to FPGA and in verilog.....during my project filter design, actually i have written program for lowpass filter of 15 order..... but i am not understanding how to implement on FPGA . i am totally confused about input portions... wat input should i take and how.....??
plz anyone provide me or kindly guide me to tackle these problems....and if anyone has simillar projects than please provide it to me for reference and help.....
your's help will be appreciated...and will be unforgatable.....,,cuz submission of my project is approaching towards me with great acceleration........
tnx
