ADC0804 interfaced with CPLD

[Altera_Forum]

Hello All, 

 I am trying to interface an ADC0804 with a CPLD. The ADC0804 has potentiometerat the input. I have successfully tested the ADC using LEDs at the output, itworked fine. I am now moving onto the next step which is to connect the digitalADC outputs to a CPLD. My question is how do I connect the CPLD system clock tothe ADC, surely only 1 common clock should be used. I have seen on the internetthat different clocks are used. One for the microcontroller device and one forthe ADC0804, this does not seem right to me. If someone could give me someadvice I would really appreciate. 

[Altera_Forum]

The ADC0804 is a pretty slow ADC (100us conversion time). Its basically designed for measuring DC values. 

 From a brief look at the data sheet  http://www.ti.com/product/adc0804  It says you can treated the interface like a microprocessor I/O device. The timing diagrams show that the read/write interface is essentially asynchronous, you just have to assert the signals for as long as the data sheet indicates - based on how you clock the thing. Since the clock is so slow and the ADC dynamic range is only 8-bits (so clock jitter is not so important), you can generate the clock using the CPLD.  Do you have a board that already contains the part, or are you just creating a proto-board interface?  Cheers, Dave

[Altera_Forum]

Thank you very much for the reply and advice. On most of the circuit diagrams I look at the RC network used to clock the ADC has the following value: C=150 pF and R=10 kohm. I am using the matrix multimedia CPLD target board which has a 25 MHz crystal. I have reduced the clock frequency to 625 KHz as read that is the most frequently speed used. I have followed the steps given on the data sheet for starting the conversion and reading the value. No success yet unfortunately. Does what I wrote see correct to you?

[Altera_Forum]

--- Quote Start ---  On most of the circuit diagrams I look at the RC network used to clock the ADC has the following value: C=150 pF and R=10 kohm.   --- Quote End ---   From the figure in the data sheet, the clock can be generated using an RC network, or you can just drive the clock pin directly from the CPLD. Personally I would drive it from the CPLD, so that you know the exact frequency.    --- Quote Start ---   I am using the matrix multimedia CPLD target board which has a 25 MHz crystal.   --- Quote End ---   Link?  The ADC is a 5V part. I sure hope your CPLD is 5V tolerant ...    --- Quote Start ---   I have reduced the clock frequency to 625 KHz as read that is the most frequently speed used. I have followed the steps given on the data sheet for starting the conversion and reading the value. No success yet unfortunately. Does what I wrote see correct to you?  --- Quote End ---    Yes, it sounds fine.  Capture some read/write traces ... you'll have to use an oscilloscope, since you are using a CPLD. If you were using an FPGA, you could use SignalTap. Alternatively, create a testbench and post Modelsim waveforms.  Cheers, Dave

[Altera_Forum]

Dave, 

  Thanks again, I am sorry the link for the hardware is below. http://www.matrixmultimedia.com/resources/files/datasheets/eb020-30-3.pdf  I feel better connected the CPLD clock frequency to the ADC. I will have a go at this tomorrow and get some output traces. Before testing it actually on the hardware.  Cheers  Jag.

[Altera_Forum]

--- Quote Start ---   Thanks again, I am sorry the link for the hardware is below. http://www.matrixmultimedia.com/resources/files/datasheets/eb020-30-3.pdf   --- Quote End ---   The CPLD is powered from 5V, so you can connect this to the ADC ok.    --- Quote Start ---   I feel better connected the CPLD clock frequency to the ADC. I will have a go at this tomorrow and get some output traces. Before testing it actually on the hardware.   --- Quote End ---   You need to create a slower speed clock in the CPLD and then connect that to the ADC. You would create the slower speed clock using a counter. The counter can be used to count the half-period of the clock you want, and then you toggle the clock output every time the counter completes (asserts carry-out). This gives you a nice square wave for the output clock.  Cheers, Dave

[Altera_Forum]

Dave, 

I am a bit confused here, I have already managed to reduced the 25 MHz to 625 KHz using a counter. Is this what you meant or do you mean I have to reduce the 625 KHz further.  Jag.

[Altera_Forum]

--- Quote Start ---   I am a bit confused here, I have already managed to reduced the 25 MHz to 625 KHz using a counter. Is this what you meant or do you mean I have to reduce the 625 KHz further.   --- Quote End ---    You stated in the message above "I feel better connected the CPLD clock frequency to the ADC", so I just wanted to make sure that you knew you needed to use a slower clock. You obviously do, so you're all set!  Cheers, Dave

[Altera_Forum]

Dave, 

I should have been more clear, mu fault. Thanks again mate for all your help. Jag.

[Altera_Forum]

--- Quote Start ---   Thanks again mate for all your help.   --- Quote End ---    No problem! Good luck with your tests.  Cheers, Dave

[Altera_Forum]

Sorry to bother you again Dave. 

 I can not get me code working, if you can could have a quick look at my code.   -- Standard libary delarations  library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- define input and outputs for the entity --Entity is the device inputs and outputs  entity convert is port( --input variable (1-bit) cs: out std_logic:='1'; rd: out std_logic:='1'; wr: out std_logic:='1'; intr: inout std_logic:='1'; digin: in std_logic_vector(7 downto 0); digout: out std_logic_vector(7 downto 0); flag: out std_logic; --buffer can be input or output conversion: in std_logic); end convert;  -- internal function of entity architecture behave of convert is --internal variable signal count2: integer range 0 to 50:=1; --signal count3: integer range 0 to 20:=1;  begin process (intr,conversion) begin -- Required in order to convert the sinewave to a square wave  -- Check for clock to occur and trigger on rising edge  if(conversion'event and conversion='1') then --increment the count variable by 1 count2<=count2+1;  if(count2 = 4) then cs<='0'; else if(count2 = 8) then wr<='0'; else if(count2 = 12) then cs<='1'; else if(intr='1') then count2<=count2; end if; if(count2 = 20) then cs<='0'; end if; if(count2 = 30) then rd<='0'; digout<=digin; end if; if(count2 = 40) then rd<='1'; end if; if(count2 = 50) then cs<='1'; count2 <= 1; end if;  -- end all the if statements end if; end if; end if; end if; --end if;  --end the process  end process; --end internal function end behave;   There is another part of the code which reduces the 25 MHz clock signal to 625 KHz. The clock out of that component is connected to conversion input. I have connected the 625 clock frequency to pin 4 of the ADC0804 and checked with Oscilliscope. I have output traces showing that code works but I am getting no outputs. Could you please, please give some advice.  Jag.

[Altera_Forum]

Just for completeness this is the reduce frequency code. 

 -- Standard libary delarations  library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  -- define input and outputs for the entity --Entity is the device inputs and outputs  entity adc is port( --input variable (1-bit)  clk_in: in std_logic; --buffer can be input or output clk_out: buffer std_logic; clk: buffer std_logic); end adc;  -- internal function of entity architecture behave of adc is --internal variable signal count: integer range 0 to 125000;  begin process (count, clk_in,clk_out) begin --signal clk_out: integer;  -- Required in order to convert the sinewave to a square wave clk_out <= not clk_in;  -- Check for clock to occur and trigger on rising edge  if(clk_out'event and clk_out='1') then --increment the count variable by 1 count <=count+1;  if (count = 20) then clk <= not clk; -- reset count variable to 1 count <= 1;  -- end all the if statements end if;  end if; --end the process end process; --end internal function end behave;  Jag.

[Altera_Forum]

Hi Jag, 

 Reading code is not a very good use of anyone's time when trying to help you.  What you need to do is to supply a testbench that can be run in Modelsim. That allows you to see the waveforms your logic is creating, and it allows the readers of this forum to help you.  I've posted several examples of testbenches before:  http://www.alteraforum.com/forum/showthread.php?t=32386&p=132149#post132149 http://www.alteraforum.com/forum/showthread.php?t=38988&p=160666#post160666 http://www.alteraforum.com/forum/showthread.php?t=35572&p=146930#post146930  Create a testbench for your code and see if it generates the waveforms you expect. Then synthesize the code to see if you get warnings.  If I was going to implement an interface to this ADC, I would create a finite state machine that was clocked by the CPLD clock. That state machine would implement the logic required to read from the device.  For example, Altera's Avalon-MM interface defines a synchronous bus with wait-states and a read-valid output.  But perhaps this is a little advanced at this point.  What is supposed to be reading this ADC?  Cheers, Dave

[Altera_Forum]

Thanks Dave, I will create a testbench as advised. The ADC has a potentiometer as the in 

put.   Jag.

[Altera_Forum]

--- Quote Start ---  I will create a testbench as advised. The ADC has a potentiometer as the input.   --- Quote End ---    Great.  What I'm trying to do here is advise you on how to approach this problem. If you get stuck, then I'll help out. Take a shot at creating the testbench and getting your code to work, and I'll check it out. If necessary, I'll make some suggestions.  What is the overall plan for this ADC. You have a potentiometer as the input to the ADC, but what does that represent (or what will it represent later on), and who or what will be reading the ADC.  The CPLD board you are using is not very powerful, so you cannot implement a NIOS II processor. Is there a microcontroller on the board that can access the FPGA logic? If so, you could program that microcontroller to access the ADC reading, and then send it to your PC.  Its a good idea to start with a system design, and then start implementing the pieces.  Cheers, Dave